
----------------------------------------------------------------
-- 
-- Created by the Synopsys Library Compiler 1999.10
-- FILENAME     :    mAMIs050DL_FTGS.vhd
-- FILE CONTENTS:    Entity, Structural Architecture(FTGS),
--                   and Configuration
-- DATE CREATED :    Thu Jun 15 18:02:53 2000
-- 
-- LIBRARY      :    mAMIs050DL
-- REVISION     :    Not Specified
-- TECHNOLOGY   :    cmos
-- TIME SCALE   :    1 ps
-- LOGIC SYSTEM :    IEEE-1164
-- NOTES        :    FTGS, Timing_mesg(TRUE), Timing_xgen(FALSE), GLITCH_HANDLE
-- HISTORY      :
-- 
----------------------------------------------------------------

----- CELL AO22 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity AO22 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 879.730 ps;
      tpdA_outb_F                    :	Time := 716.920 ps;
      tpdB_outb_R                    :	Time := 940.160 ps;
      tpdB_outb_F                    :	Time := 729.560 ps;
      tpdC_outb_R                    :	Time := 640.380 ps;
      tpdC_outb_F                    :	Time := 534.000 ps;
      tpdD_outb_R                    :	Time := 622.660 ps;
      tpdD_outb_F                    :	Time := 551.380 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end AO22;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of AO22 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_outb_F: constant is 
	"U5/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_outb_R: constant is 
	"U5/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is 
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is 
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is 
	"U5/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U5/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U5/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U4/delay(TRAN_10), " &
	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U4/delay(TRAN_01), " &
	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdC_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdC_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdC_R, twdC_F, twdC_R, twdC_R, twdC_F, twdC_F))
	port map( Input => C, Output => connect(2));

   U4 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(3));

   -- Netlist
   U5 : TLU
	generic map(
		N => 4,
		TruthTable => "0001000100011111",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C D outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_outb_R, tpdB_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_outb_R, tpdC_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_outb_R, tpdD_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Input(3) => connect(3), 
		Output => outb);


end FTGS;

configuration CFG_AO22_FTGS of AO22 is
   for FTGS
   end for;
end CFG_AO22_FTGS;


----- CELL AOI22 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity AOI22 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 424.960 ps;
      tpdA_outb_F                    :	Time := 485.330 ps;
      tpdB_outb_R                    :	Time := 413.220 ps;
      tpdB_outb_F                    :	Time := 479.170 ps;
      tpdC_outb_R                    :	Time := 218.800 ps;
      tpdC_outb_F                    :	Time := 236.940 ps;
      tpdD_outb_R                    :	Time := 233.150 ps;
      tpdD_outb_F                    :	Time := 246.650 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end AOI22;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of AOI22 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_outb_F: constant is 
	"U5/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_outb_R: constant is 
	"U5/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is 
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is 
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is 
	"U5/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U5/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U5/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U4/delay(TRAN_10), " &
	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U4/delay(TRAN_01), " &
	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdC_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdC_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdC_R, twdC_F, twdC_R, twdC_R, twdC_F, twdC_F))
	port map( Input => C, Output => connect(2));

   U4 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(3));

   -- Netlist
   U5 : TLU
	generic map(
		N => 4,
		TruthTable => "1110111011100000",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C D outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_outb_R, tpdB_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_outb_R, tpdC_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_outb_R, tpdD_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Input(3) => connect(3), 
		Output => outb);


end FTGS;

configuration CFG_AOI22_FTGS of AOI22 is
   for FTGS
   end for;
end CFG_AOI22_FTGS;


----- CELL BUF1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity BUF1 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 336.960 ps;
      tpdA_outb_F                    :	Time := 352.160 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end BUF1;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of BUF1 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U2/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U2/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   -- Netlist
   U2 : TLU
	generic map(
		N => 1,
		TruthTable => "01",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A outb",
		delay_param =>
			( 0 => (tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "X",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Output => outb);


end FTGS;

configuration CFG_BUF1_FTGS of BUF1 is
   for FTGS
   end for;
end CFG_BUF1_FTGS;


----- CELL BUF4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity BUF4 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 427.380 ps;
      tpdA_outb_F                    :	Time := 517.550 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end BUF4;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of BUF4 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U2/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U2/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   -- Netlist
   U2 : TLU
	generic map(
		N => 1,
		TruthTable => "01",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A outb",
		delay_param =>
			( 0 => (tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "X",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Output => outb);


end FTGS;

configuration CFG_BUF4_FTGS of BUF4 is
   for FTGS
   end for;
end CFG_BUF4_FTGS;


----- CELL BUFI4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity BUFI4 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 88.510 ps;
      tpdA_outb_F                    :	Time := 88.290 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end BUFI4;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of BUFI4 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U2/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U2/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   -- Netlist
   U2 : TLU
	generic map(
		N => 1,
		TruthTable => "10",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A outb",
		delay_param =>
			( 0 => (tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "X",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Output => outb);


end FTGS;

configuration CFG_BUFI4_FTGS of BUFI4 is
   for FTGS
   end for;
end CFG_BUFI4_FTGS;


----- CELL BUFZ -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity BUFZ is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 833.610 ps;
      tpdA_outb_F                    :	Time := 752.680 ps;
      tpdOEB_outb_R                  :	Time := 291.490 ps;
      tpdOEB_outb_F                  :	Time := 193.780 ps;
      tpdOEB_outb_LZ                 :	Time := 291.490 ps;
      tpdOEB_outb_HZ                 :	Time := 193.780 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdOEB_R                       :	Time := 0.000 ps;
      twdOEB_F                       :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      OEB                            :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end BUFZ;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of BUFZ is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdOEB_outb_HZ: constant is 
	"U3/delay_param(1)(TRAN_1Z)";
   attribute PROPAGATE_VALUE of tpdOEB_outb_LZ: constant is 
	"U3/delay_param(1)(TRAN_0Z)";
   attribute PROPAGATE_VALUE of tpdOEB_outb_F: constant is 
	"U3/delay_param(1)(TRAN_10), " &
	"U3/delay_param(1)(TRAN_Z0)";
   attribute PROPAGATE_VALUE of tpdOEB_outb_R: constant is 
	"U3/delay_param(1)(TRAN_01), " &
	"U3/delay_param(1)(TRAN_Z1)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U3/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U3/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdOEB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdOEB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdOEB_R, twdOEB_F, twdOEB_R, twdOEB_R, twdOEB_F, twdOEB_F))
	port map( Input => OEB, Output => connect(1));

   -- Netlist
   U3 : TLU
	generic map(
		N => 2,
		TruthTable => "0Z1Z",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A OEB outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdOEB_outb_R, tpdOEB_outb_F, tpdOEB_outb_LZ, tpdOEB_outb_R, tpdOEB_outb_HZ, tpdOEB_outb_F)),
		InMapZ => "XX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Output => outb);


end FTGS;

configuration CFG_BUFZ_FTGS of BUFZ is
   for FTGS
   end for;
end CFG_BUFZ_FTGS;


----- CELL DFF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity DFF is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdCLK_Q_R                     :	Time := 1763.660 ps;
      tpdCLK_Q_F                     :	Time := 1535.840 ps;
      tpdCLK_QB_R                    :	Time := 1293.840 ps;
      tpdCLK_QB_F                    :	Time := 1513.420 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 450.000 ps;
      twCLK_H                        :	Time := 750.000 ps;
      twCLK_L                        :	Time := 750.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end DFF;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of DFF is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdCLK_QB_F: constant is 
	"U4/delay_param(0)(TRAN_10), " &
	"U4/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLK_QB_R: constant is 
	"U4/delay_param(0)(TRAN_01), " &
	"U4/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of twCLK_L: constant is 
	"U3/constraint_param(3).Check_time, " &
	"U4/constraint_param(3).Check_time";
   attribute PROPAGATE_VALUE of twCLK_H: constant is 
	"U3/constraint_param(2).Check_time, " &
	"U4/constraint_param(2).Check_time";
   attribute PROPAGATE_VALUE of tsuD_CLK: constant is 
	"U3/constraint_param(1).Check_time, " &
	"U4/constraint_param(1).Check_time";
   attribute PROPAGATE_VALUE of thCLK_D: constant is 
	"U3/constraint_param(0).Check_time, " &
	"U4/constraint_param(0).Check_time";
   attribute PROPAGATE_VALUE of tpdCLK_Q_F: constant is 
	"U3/delay_param(0)(TRAN_10), " &
	"U3/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLK_Q_R: constant is 
	"U3/delay_param(0)(TRAN_01), " &
	"U3/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdCLK_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdCLK_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdCLK_R, twdCLK_F, twdCLK_R, twdCLK_R, twdCLK_F, twdCLK_F))
	port map( Input => CLK, Output => connect(1));

   -- Netlist
   U3 : SEQGEN
	generic map(
		N_enable => 0,
		N_clock => 1,
		N_clear => 0,
		N_preset => 0,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "",
		lut_clock => "01",
		lut_clear => "",
		lut_preset => "",
		lut_data => "01",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN01NN01",
		pin_names => "CLK D Q",
		delay_param =>
			((tpdCLK_Q_R, tpdCLK_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLK_Q_R, tpdCLK_Q_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => 
			((0, 1, hold_rising_ff, thCLK_D),
			 (1, 0, setup_rising_ff, tsuD_CLK),
			 (0, 0, pwidth_pos_hi_ff, twCLK_H),
			 (0, 0, pwidth_neg_hi_ff, twCLK_L)),
		InMapZ => "XX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => Timing_mesg,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(1),
			Input(1) => connect(0),
			Output => Q);

   U4 : SEQGEN
	generic map(
		N_enable => 0,
		N_clock => 1,
		N_clear => 0,
		N_preset => 0,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "",
		lut_clock => "01",
		lut_clear => "",
		lut_preset => "",
		lut_data => "10",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN01NN01",
		pin_names => "CLK D QB",
		delay_param =>
			((tpdCLK_QB_R, tpdCLK_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLK_QB_R, tpdCLK_QB_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => 
			((0, 1, hold_rising_ff, thCLK_D),
			 (1, 0, setup_rising_ff, tsuD_CLK),
			 (0, 0, pwidth_pos_hi_ff, twCLK_H),
			 (0, 0, pwidth_neg_hi_ff, twCLK_L)),
		InMapZ => "XX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => FALSE,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(1),
			Input(1) => connect(0),
			Output => QB);


end FTGS;

configuration CFG_DFF_FTGS of DFF is
   for FTGS
   end for;
end CFG_DFF_FTGS;


----- CELL DFFC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity DFFC is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdCLB_Q_F                     :	Time := 590.630 ps;
      tpdCLK_Q_R                     :	Time := 2426.230 ps;
      tpdCLK_Q_F                     :	Time := 1898.930 ps;
      tpdCLB_QB_R                    :	Time := 100.000 ps;
      tpdCLB_QB_F                    :	Time := 2272.700 ps;
      tpdCLK_QB_R                    :	Time := 1424.740 ps;
      tpdCLK_QB_F                    :	Time := 1736.000 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 560.000 ps;
      twCLK_H                        :	Time := 980.000 ps;
      twCLK_L                        :	Time := 980.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end DFFC;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of DFFC is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdCLB_QB_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLB_QB_R: constant is 
	"U5/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdCLK_QB_F: constant is 
	"U5/delay_param(0)(TRAN_10), " &
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLK_QB_R: constant is 
	"U5/delay_param(0)(TRAN_01), " &
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of twCLK_L: constant is 
	"U4/constraint_param(3).Check_time, " &
	"U5/constraint_param(3).Check_time";
   attribute PROPAGATE_VALUE of twCLK_H: constant is 
	"U4/constraint_param(2).Check_time, " &
	"U5/constraint_param(2).Check_time";
   attribute PROPAGATE_VALUE of tsuD_CLK: constant is 
	"U4/constraint_param(1).Check_time, " &
	"U5/constraint_param(1).Check_time";
   attribute PROPAGATE_VALUE of thCLK_D: constant is 
	"U4/constraint_param(0).Check_time, " &
	"U5/constraint_param(0).Check_time";
   attribute PROPAGATE_VALUE of tpdCLB_Q_F: constant is 
	"U4/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLK_Q_F: constant is 
	"U4/delay_param(0)(TRAN_10), " &
	"U4/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLK_Q_R: constant is 
	"U4/delay_param(0)(TRAN_01), " &
	"U4/delay_param(1)(TRAN_01), U4/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdCLB_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdCLB_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdCLK_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdCLK_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(1));

   U2 : WIREBUF
	generic map(delay => (twdCLK_R, twdCLK_F, twdCLK_R, twdCLK_R, twdCLK_F, twdCLK_F))
	port map( Input => CLK, Output => connect(2));

   U3 : WIREBUF
	generic map(delay => (twdCLB_R, twdCLB_F, twdCLB_R, twdCLB_R, twdCLB_F, twdCLB_F))
	port map( Input => CLB, Output => connect(0));

   -- Netlist
   U4 : SEQGEN
	generic map(
		N_enable => 0,
		N_clock => 1,
		N_clear => 1,
		N_preset => 0,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "",
		lut_clock => "01",
		lut_clear => "10",
		lut_preset => "",
		lut_data => "01",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN000100NN000100",
		pin_names => "CLK CLB D Q",
		delay_param =>
			((tpdCLK_Q_R, tpdCLK_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLK_Q_R, tpdCLB_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLK_Q_R, tpdCLK_Q_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => 
			((0, 2, hold_rising_ff, thCLK_D),
			 (2, 0, setup_rising_ff, tsuD_CLK),
			 (0, 0, pwidth_pos_hi_ff, twCLK_H),
			 (0, 0, pwidth_neg_hi_ff, twCLK_L)),
		InMapZ => "XXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => Timing_mesg,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(2),
			Input(1) => connect(0),
			Input(2) => connect(1),
			Output => Q);

   U5 : SEQGEN
	generic map(
		N_enable => 0,
		N_clock => 1,
		N_clear => 1,
		N_preset => 0,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "",
		lut_clock => "01",
		lut_clear => "10",
		lut_preset => "",
		lut_data => "10",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN110111NN110111",
		pin_names => "CLK CLB D QB",
		delay_param =>
			((tpdCLK_QB_R, tpdCLK_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLB_QB_R, tpdCLB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLK_QB_R, tpdCLK_QB_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => 
			((0, 2, hold_rising_ff, thCLK_D),
			 (2, 0, setup_rising_ff, tsuD_CLK),
			 (0, 0, pwidth_pos_hi_ff, twCLK_H),
			 (0, 0, pwidth_neg_hi_ff, twCLK_L)),
		InMapZ => "XXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => FALSE,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(2),
			Input(1) => connect(0),
			Input(2) => connect(1),
			Output => QB);


end FTGS;

configuration CFG_DFFC_FTGS of DFFC is
   for FTGS
   end for;
end CFG_DFFC_FTGS;


----- CELL DFFP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity DFFP is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdPRB_Q_R                     :	Time := 806.750 ps;
      tpdCLK_Q_R                     :	Time := 1984.310 ps;
      tpdCLK_Q_F                     :	Time := 1904.280 ps;
      tpdPRB_QB_F                    :	Time := 477.540 ps;
      tpdCLK_QB_R                    :	Time := 1542.680 ps;
      tpdCLK_QB_F                    :	Time := 1658.400 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 460.000 ps;
      twCLK_H                        :	Time := 880.000 ps;
      twCLK_L                        :	Time := 880.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end DFFP;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of DFFP is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdPRB_QB_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLK_QB_F: constant is 
	"U5/delay_param(0)(TRAN_10), " &
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLK_QB_R: constant is 
	"U5/delay_param(0)(TRAN_01), " &
	"U5/delay_param(1)(TRAN_01), U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of twCLK_L: constant is 
	"U4/constraint_param(3).Check_time, " &
	"U5/constraint_param(3).Check_time";
   attribute PROPAGATE_VALUE of twCLK_H: constant is 
	"U4/constraint_param(2).Check_time, " &
	"U5/constraint_param(2).Check_time";
   attribute PROPAGATE_VALUE of tsuD_CLK: constant is 
	"U4/constraint_param(1).Check_time, " &
	"U5/constraint_param(1).Check_time";
   attribute PROPAGATE_VALUE of thCLK_D: constant is 
	"U4/constraint_param(0).Check_time, " &
	"U5/constraint_param(0).Check_time";
   attribute PROPAGATE_VALUE of tpdPRB_Q_R: constant is 
	"U4/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdCLK_Q_F: constant is 
	"U4/delay_param(0)(TRAN_10), " &
	"U4/delay_param(1)(TRAN_10), U4/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLK_Q_R: constant is 
	"U4/delay_param(0)(TRAN_01), " &
	"U4/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdPRB_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdPRB_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdCLK_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdCLK_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(1));

   U2 : WIREBUF
	generic map(delay => (twdCLK_R, twdCLK_F, twdCLK_R, twdCLK_R, twdCLK_F, twdCLK_F))
	port map( Input => CLK, Output => connect(2));

   U3 : WIREBUF
	generic map(delay => (twdPRB_R, twdPRB_F, twdPRB_R, twdPRB_R, twdPRB_F, twdPRB_F))
	port map( Input => PRB, Output => connect(0));

   -- Netlist
   U4 : SEQGEN
	generic map(
		N_enable => 0,
		N_clock => 1,
		N_clear => 0,
		N_preset => 1,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "",
		lut_clock => "01",
		lut_clear => "",
		lut_preset => "10",
		lut_data => "01",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN110111NN110111",
		pin_names => "CLK PRB D Q",
		delay_param =>
			((tpdCLK_Q_R, tpdCLK_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdPRB_Q_R, tpdCLK_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLK_Q_R, tpdCLK_Q_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => 
			((0, 2, hold_rising_ff, thCLK_D),
			 (2, 0, setup_rising_ff, tsuD_CLK),
			 (0, 0, pwidth_pos_hi_ff, twCLK_H),
			 (0, 0, pwidth_neg_hi_ff, twCLK_L)),
		InMapZ => "XXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => Timing_mesg,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(2),
			Input(1) => connect(0),
			Input(2) => connect(1),
			Output => Q);

   U5 : SEQGEN
	generic map(
		N_enable => 0,
		N_clock => 1,
		N_clear => 0,
		N_preset => 1,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "",
		lut_clock => "01",
		lut_clear => "",
		lut_preset => "10",
		lut_data => "10",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN000100NN000100",
		pin_names => "CLK PRB D QB",
		delay_param =>
			((tpdCLK_QB_R, tpdCLK_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLK_QB_R, tpdPRB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLK_QB_R, tpdCLK_QB_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => 
			((0, 2, hold_rising_ff, thCLK_D),
			 (2, 0, setup_rising_ff, tsuD_CLK),
			 (0, 0, pwidth_pos_hi_ff, twCLK_H),
			 (0, 0, pwidth_neg_hi_ff, twCLK_L)),
		InMapZ => "XXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => FALSE,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(2),
			Input(1) => connect(0),
			Input(2) => connect(1),
			Output => QB);


end FTGS;

configuration CFG_DFFP_FTGS of DFFP is
   for FTGS
   end for;
end CFG_DFFP_FTGS;


----- CELL DFFPC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity DFFPC is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdPRB_Q_R                     :	Time := 1152.300 ps;
      tpdCLB_Q_F                     :	Time := 514.590 ps;
      tpdCLK_Q_R                     :	Time := 2547.160 ps;
      tpdCLK_Q_F                     :	Time := 2043.240 ps;
      tpdPRB_QB_F                    :	Time := 419.190 ps;
      tpdCLB_QB_R                    :	Time := 1587.030 ps;
      tpdCLK_QB_R                    :	Time := 1556.220 ps;
      tpdCLK_QB_F                    :	Time := 1901.760 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 512.970 ps;
      twCLK_H                        :	Time := 1050.000 ps;
      twCLK_L                        :	Time := 1050.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end DFFPC;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of DFFPC is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdPRB_QB_F: constant is 
	"U6/delay_param(1)(TRAN_10), " &
	"U6/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLB_QB_R: constant is 
	"U6/delay_param(1)(TRAN_01), " &
	"U6/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdCLK_QB_F: constant is 
	"U6/delay_param(0)(TRAN_10), " &
	"U6/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLK_QB_R: constant is 
	"U6/delay_param(0)(TRAN_01), " &
	"U6/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of twCLK_L: constant is 
	"U5/constraint_param(3).Check_time, " &
	"U6/constraint_param(3).Check_time";
   attribute PROPAGATE_VALUE of twCLK_H: constant is 
	"U5/constraint_param(2).Check_time, " &
	"U6/constraint_param(2).Check_time";
   attribute PROPAGATE_VALUE of tsuD_CLK: constant is 
	"U5/constraint_param(1).Check_time, " &
	"U6/constraint_param(1).Check_time";
   attribute PROPAGATE_VALUE of thCLK_D: constant is 
	"U5/constraint_param(0).Check_time, " &
	"U6/constraint_param(0).Check_time";
   attribute PROPAGATE_VALUE of tpdCLB_Q_F: constant is 
	"U5/delay_param(1)(TRAN_10), " &
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdPRB_Q_R: constant is 
	"U5/delay_param(1)(TRAN_01), " &
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdCLK_Q_F: constant is 
	"U5/delay_param(0)(TRAN_10), " &
	"U5/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLK_Q_R: constant is 
	"U5/delay_param(0)(TRAN_01), " &
	"U5/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdCLB_F: constant is 
	"U4/delay(TRAN_10), " &
	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdCLB_R: constant is 
	"U4/delay(TRAN_01), " &
	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdPRB_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdPRB_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdCLK_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdCLK_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(2));

   U2 : WIREBUF
	generic map(delay => (twdCLK_R, twdCLK_F, twdCLK_R, twdCLK_R, twdCLK_F, twdCLK_F))
	port map( Input => CLK, Output => connect(3));

   U3 : WIREBUF
	generic map(delay => (twdPRB_R, twdPRB_F, twdPRB_R, twdPRB_R, twdPRB_F, twdPRB_F))
	port map( Input => PRB, Output => connect(0));

   U4 : WIREBUF
	generic map(delay => (twdCLB_R, twdCLB_F, twdCLB_R, twdCLB_R, twdCLB_F, twdCLB_F))
	port map( Input => CLB, Output => connect(1));

   -- Netlist
   U5 : SEQGEN
	generic map(
		N_enable => 0,
		N_clock => 1,
		N_clear => 1,
		N_preset => 1,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "",
		lut_clock => "01",
		lut_clear => "10",
		lut_preset => "10",
		lut_data => "01",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN11001101110011" &
		            "NN11001101110011",
		pin_names => "CLK CLB PRB D Q",
		delay_param =>
			((tpdCLK_Q_R, tpdCLK_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdPRB_Q_R, tpdCLB_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdPRB_Q_R, tpdCLB_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLK_Q_R, tpdCLK_Q_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => 
			((0, 3, hold_rising_ff, thCLK_D),
			 (3, 0, setup_rising_ff, tsuD_CLK),
			 (0, 0, pwidth_pos_hi_ff, twCLK_H),
			 (0, 0, pwidth_neg_hi_ff, twCLK_L)),
		InMapZ => "XXXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => Timing_mesg,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(3),
			Input(1) => connect(1),
			Input(2) => connect(0),
			Input(3) => connect(2),
			Output => Q);

   U6 : SEQGEN
	generic map(
		N_enable => 0,
		N_clock => 1,
		N_clear => 1,
		N_preset => 1,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "",
		lut_clock => "01",
		lut_clear => "10",
		lut_preset => "10",
		lut_data => "10",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN00111101001111" &
		            "NN00111101001111",
		pin_names => "CLK CLB PRB D QB",
		delay_param =>
			((tpdCLK_QB_R, tpdCLK_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLB_QB_R, tpdPRB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLB_QB_R, tpdPRB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLK_QB_R, tpdCLK_QB_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => 
			((0, 3, hold_rising_ff, thCLK_D),
			 (3, 0, setup_rising_ff, tsuD_CLK),
			 (0, 0, pwidth_pos_hi_ff, twCLK_H),
			 (0, 0, pwidth_neg_hi_ff, twCLK_L)),
		InMapZ => "XXXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => FALSE,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(3),
			Input(1) => connect(1),
			Input(2) => connect(0),
			Input(3) => connect(2),
			Output => QB);


end FTGS;

configuration CFG_DFFPC_FTGS of DFFPC is
   for FTGS
   end for;
end CFG_DFFPC_FTGS;


----- CELL INV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity INV is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 147.050 ps;
      tpdA_outb_F                    :	Time := 131.020 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end INV;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of INV is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U2/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U2/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   -- Netlist
   U2 : TLU
	generic map(
		N => 1,
		TruthTable => "10",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A outb",
		delay_param =>
			( 0 => (tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "X",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Output => outb);


end FTGS;

configuration CFG_INV_FTGS of INV is
   for FTGS
   end for;
end CFG_INV_FTGS;


----- CELL INV2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity INV2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 143.010 ps;
      tpdA_out1_F                    :	Time := 133.030 ps;
      tpdB_out2_R                    :	Time := 142.700 ps;
      tpdB_out2_F                    :	Time := 132.800 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end INV2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of INV2 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is 
	"U4/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is 
	"U4/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is 
	"U3/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is 
	"U3/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   -- Netlist
   U3 : TLU
	generic map(
		N => 1,
		TruthTable => "10",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A out1",
		delay_param =>
			( 0 => (tpdA_out1_R, tpdA_out1_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "X",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Output => out1);

   U4 : TLU
	generic map(
		N => 1,
		TruthTable => "10",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "B out2",
		delay_param =>
			( 0 => (tpdB_out2_R, tpdB_out2_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "X",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(1), 
		Output => out2);


end FTGS;

configuration CFG_INV2_FTGS of INV2 is
   for FTGS
   end for;
end CFG_INV2_FTGS;


----- CELL INVZ -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity INVZ is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdOEB_outb_R                  :	Time := 0.000 ps;
      tpdOEB_outb_F                  :	Time := 172.430 ps;
      tpdOEB_outb_LZ                 :	Time := 0.000 ps;
      tpdOEB_outb_HZ                 :	Time := 172.430 ps;
      tpdA_outb_R                    :	Time := 204.660 ps;
      tpdA_outb_F                    :	Time := 191.380 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdOEB_R                       :	Time := 0.000 ps;
      twdOEB_F                       :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      OEB                            :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end INVZ;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of INVZ is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdOEB_outb_HZ: constant is 
	"U3/delay_param(1)(TRAN_1Z)";
   attribute PROPAGATE_VALUE of tpdOEB_outb_LZ: constant is 
	"U3/delay_param(1)(TRAN_0Z)";
   attribute PROPAGATE_VALUE of tpdOEB_outb_F: constant is 
	"U3/delay_param(1)(TRAN_10), " &
	"U3/delay_param(1)(TRAN_Z0)";
   attribute PROPAGATE_VALUE of tpdOEB_outb_R: constant is 
	"U3/delay_param(1)(TRAN_01), " &
	"U3/delay_param(1)(TRAN_Z1)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U3/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U3/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdOEB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdOEB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(1));

   U2 : WIREBUF
	generic map(delay => (twdOEB_R, twdOEB_F, twdOEB_R, twdOEB_R, twdOEB_F, twdOEB_F))
	port map( Input => OEB, Output => connect(0));

   -- Netlist
   U3 : TLU
	generic map(
		N => 2,
		TruthTable => "Z0Z1",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A OEB outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdOEB_outb_R, tpdOEB_outb_F, tpdOEB_outb_LZ, tpdOEB_outb_R, tpdOEB_outb_HZ, tpdOEB_outb_F)),
		InMapZ => "XX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(1), 
		Input(1) => connect(0), 
		Output => outb);


end FTGS;

configuration CFG_INVZ_FTGS of INVZ is
   for FTGS
   end for;
end CFG_INVZ_FTGS;


----- CELL LAT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity LAT is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdD_Q_R                       :	Time := 747.850 ps;
      tpdD_Q_F                       :	Time := 775.010 ps;
      tpdGB_Q_R                      :	Time := 1219.200 ps;
      tpdGB_Q_F                      :	Time := 1031.260 ps;
      tpdD_QB_R                      :	Time := 1019.590 ps;
      tpdD_QB_F                      :	Time := 950.320 ps;
      tpdGB_QB_R                     :	Time := 1434.270 ps;
      tpdGB_QB_F                     :	Time := 1227.970 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end LAT;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of LAT is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_QB_F: constant is 
	"U4/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_QB_R: constant is 
	"U4/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdGB_QB_F: constant is 
	"U4/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdGB_QB_R: constant is 
	"U4/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdD_Q_F: constant is 
	"U3/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_Q_R: constant is 
	"U3/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdGB_Q_F: constant is 
	"U3/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdGB_Q_R: constant is 
	"U3/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdGB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdGB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdGB_R, twdGB_F, twdGB_R, twdGB_R, twdGB_F, twdGB_F))
	port map( Input => GB, Output => connect(1));

   -- Netlist
   U3 : SEQGEN
	generic map(
		N_enable => 1,
		N_clock => 0,
		N_clear => 0,
		N_preset => 0,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "10",
		lut_clock => "",
		lut_clear => "",
		lut_preset => "",
		lut_data => "01",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN01NN01",
		pin_names => "GB D Q",
		delay_param =>
			((tpdGB_Q_R, tpdGB_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_Q_R, tpdD_Q_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => nil_constraint,
		InMapZ => "XX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => Timing_mesg,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(1),
			Input(1) => connect(0),
			Output => Q);

   U4 : SEQGEN
	generic map(
		N_enable => 1,
		N_clock => 0,
		N_clear => 0,
		N_preset => 0,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "10",
		lut_clock => "",
		lut_clear => "",
		lut_preset => "",
		lut_data => "10",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN01NN01",
		pin_names => "GB D QB",
		delay_param =>
			((tpdGB_QB_R, tpdGB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_QB_R, tpdD_QB_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => nil_constraint,
		InMapZ => "XX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => FALSE,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(1),
			Input(1) => connect(0),
			Output => QB);


end FTGS;

configuration CFG_LAT_FTGS of LAT is
   for FTGS
   end for;
end CFG_LAT_FTGS;


----- CELL LATC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity LATC is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdD_Q_R                       :	Time := 1284.890 ps;
      tpdD_Q_F                       :	Time := 1170.820 ps;
      tpdGB_Q_R                      :	Time := 1222.430 ps;
      tpdGB_Q_F                      :	Time := 1585.660 ps;
      tpdCLB_Q_F                     :	Time := 390.060 ps;
      tpdD_QB_R                      :	Time := 976.820 ps;
      tpdD_QB_F                      :	Time := 1002.540 ps;
      tpdGB_QB_R                     :	Time := 1032.910 ps;
      tpdGB_QB_F                     :	Time := 1297.520 ps;
      tpdCLB_QB_F                    :	Time := 201.080 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end LATC;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of LATC is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_QB_F: constant is 
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_QB_R: constant is 
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdCLB_QB_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdGB_QB_F: constant is 
	"U5/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdGB_QB_R: constant is 
	"U5/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdD_Q_F: constant is 
	"U4/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_Q_R: constant is 
	"U4/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdCLB_Q_F: constant is 
	"U4/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdGB_Q_F: constant is 
	"U4/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdGB_Q_R: constant is 
	"U4/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdCLB_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdCLB_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdGB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdGB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdGB_R, twdGB_F, twdGB_R, twdGB_R, twdGB_F, twdGB_F))
	port map( Input => GB, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdCLB_R, twdCLB_F, twdCLB_R, twdCLB_R, twdCLB_F, twdCLB_F))
	port map( Input => CLB, Output => connect(2));

   -- Netlist
   U4 : SEQGEN
	generic map(
		N_enable => 1,
		N_clock => 0,
		N_clear => 1,
		N_preset => 0,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "10",
		lut_clock => "",
		lut_clear => "10",
		lut_preset => "",
		lut_data => "01",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN000100NN000100",
		pin_names => "GB CLB D Q",
		delay_param =>
			((tpdGB_Q_R, tpdGB_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (0 ps, tpdCLB_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_Q_R, tpdD_Q_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => nil_constraint,
		InMapZ => "XXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => Timing_mesg,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(1),
			Input(1) => connect(2),
			Input(2) => connect(0),
			Output => Q);

   U5 : SEQGEN
	generic map(
		N_enable => 1,
		N_clock => 0,
		N_clear => 1,
		N_preset => 0,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "10",
		lut_clock => "",
		lut_clear => "10",
		lut_preset => "",
		lut_data => "10",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN110111NN110111",
		pin_names => "GB CLB D QB",
		delay_param =>
			((tpdGB_QB_R, tpdGB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (0 ps, tpdCLB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_QB_R, tpdD_QB_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => nil_constraint,
		InMapZ => "XXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => FALSE,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(1),
			Input(1) => connect(2),
			Input(2) => connect(0),
			Output => QB);


end FTGS;

configuration CFG_LATC_FTGS of LATC is
   for FTGS
   end for;
end CFG_LATC_FTGS;


----- CELL LATP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity LATP is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdD_Q_R                       :	Time := 776.950 ps;
      tpdD_Q_F                       :	Time := 850.480 ps;
      tpdGB_Q_R                      :	Time := 1277.980 ps;
      tpdGB_Q_F                      :	Time := 1063.400 ps;
      tpdPRB_Q_R                     :	Time := 196.360 ps;
      tpdD_QB_R                      :	Time := 1145.520 ps;
      tpdD_QB_F                      :	Time := 980.720 ps;
      tpdGB_QB_R                     :	Time := 1517.700 ps;
      tpdGB_QB_F                     :	Time := 1247.490 ps;
      tpdPRB_QB_R                    :	Time := 100.000 ps;
      tpdPRB_QB_F                    :	Time := 388.620 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end LATP;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of LATP is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_QB_F: constant is 
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_QB_R: constant is 
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdPRB_QB_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdPRB_QB_R: constant is 
	"U5/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdGB_QB_F: constant is 
	"U5/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdGB_QB_R: constant is 
	"U5/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdD_Q_F: constant is 
	"U4/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_Q_R: constant is 
	"U4/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdPRB_Q_R: constant is 
	"U4/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdGB_Q_F: constant is 
	"U4/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdGB_Q_R: constant is 
	"U4/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdPRB_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdPRB_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdGB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdGB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdGB_R, twdGB_F, twdGB_R, twdGB_R, twdGB_F, twdGB_F))
	port map( Input => GB, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdPRB_R, twdPRB_F, twdPRB_R, twdPRB_R, twdPRB_F, twdPRB_F))
	port map( Input => PRB, Output => connect(2));

   -- Netlist
   U4 : SEQGEN
	generic map(
		N_enable => 1,
		N_clock => 0,
		N_clear => 0,
		N_preset => 1,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "10",
		lut_clock => "",
		lut_clear => "",
		lut_preset => "10",
		lut_data => "01",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN110111NN110111",
		pin_names => "GB PRB D Q",
		delay_param =>
			((tpdGB_Q_R, tpdGB_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdPRB_Q_R, 0 ps, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_Q_R, tpdD_Q_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => nil_constraint,
		InMapZ => "XXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => Timing_mesg,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(1),
			Input(1) => connect(2),
			Input(2) => connect(0),
			Output => Q);

   U5 : SEQGEN
	generic map(
		N_enable => 1,
		N_clock => 0,
		N_clear => 0,
		N_preset => 1,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "10",
		lut_clock => "",
		lut_clear => "",
		lut_preset => "10",
		lut_data => "10",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN000100NN000100",
		pin_names => "GB PRB D QB",
		delay_param =>
			((tpdGB_QB_R, tpdGB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdPRB_QB_R, tpdPRB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_QB_R, tpdD_QB_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => nil_constraint,
		InMapZ => "XXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => FALSE,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(1),
			Input(1) => connect(2),
			Input(2) => connect(0),
			Output => QB);


end FTGS;

configuration CFG_LATP_FTGS of LATP is
   for FTGS
   end for;
end CFG_LATP_FTGS;


----- CELL LATPC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity LATPC is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdD_Q_R                       :	Time := 961.030 ps;
      tpdD_Q_F                       :	Time := 954.510 ps;
      tpdGB_Q_R                      :	Time := 1399.670 ps;
      tpdGB_Q_F                      :	Time := 1244.420 ps;
      tpdPRB_Q_R                     :	Time := 279.160 ps;
      tpdCLB_Q_F                     :	Time := 625.340 ps;
      tpdD_QB_R                      :	Time := 1264.200 ps;
      tpdD_QB_F                      :	Time := 1219.990 ps;
      tpdGB_QB_R                     :	Time := 1687.280 ps;
      tpdGB_QB_F                     :	Time := 1484.680 ps;
      tpdPRB_QB_R                    :	Time := 100.000 ps;
      tpdPRB_QB_F                    :	Time := 489.970 ps;
      tpdCLB_QB_R                    :	Time := 907.590 ps;
      tpdCLB_QB_F                    :	Time := 100.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end LATPC;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of LATPC is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_QB_F: constant is 
	"U6/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_QB_R: constant is 
	"U6/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdPRB_QB_F: constant is 
	"U6/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdPRB_QB_R: constant is 
	"U6/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdCLB_QB_F: constant is 
	"U6/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdCLB_QB_R: constant is 
	"U6/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdGB_QB_F: constant is 
	"U6/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdGB_QB_R: constant is 
	"U6/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdD_Q_F: constant is 
	"U5/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_Q_R: constant is 
	"U5/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdCLB_Q_F: constant is 
	"U5/delay_param(1)(TRAN_10), " &
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdPRB_Q_R: constant is 
	"U5/delay_param(1)(TRAN_01), " &
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdGB_Q_F: constant is 
	"U5/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdGB_Q_R: constant is 
	"U5/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdCLB_F: constant is 
	"U4/delay(TRAN_10), " &
	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdCLB_R: constant is 
	"U4/delay(TRAN_01), " &
	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdPRB_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdPRB_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdGB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdGB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdGB_R, twdGB_F, twdGB_R, twdGB_R, twdGB_F, twdGB_F))
	port map( Input => GB, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdPRB_R, twdPRB_F, twdPRB_R, twdPRB_R, twdPRB_F, twdPRB_F))
	port map( Input => PRB, Output => connect(2));

   U4 : WIREBUF
	generic map(delay => (twdCLB_R, twdCLB_F, twdCLB_R, twdCLB_R, twdCLB_F, twdCLB_F))
	port map( Input => CLB, Output => connect(3));

   -- Netlist
   U5 : SEQGEN
	generic map(
		N_enable => 1,
		N_clock => 0,
		N_clear => 1,
		N_preset => 1,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "10",
		lut_clock => "",
		lut_clear => "10",
		lut_preset => "10",
		lut_data => "01",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN11001101110011" &
		            "NN11001101110011",
		pin_names => "GB CLB PRB D Q",
		delay_param =>
			((tpdGB_Q_R, tpdGB_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdPRB_Q_R, tpdCLB_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdPRB_Q_R, tpdCLB_Q_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_Q_R, tpdD_Q_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => nil_constraint,
		InMapZ => "XXXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => Timing_mesg,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(1),
			Input(1) => connect(3),
			Input(2) => connect(2),
			Input(3) => connect(0),
			Output => Q);

   U6 : SEQGEN
	generic map(
		N_enable => 1,
		N_clock => 0,
		N_clear => 1,
		N_preset => 1,
		N_data => 1,
		N_cond_signal => 0,
		lut_enable => "10",
		lut_clock => "",
		lut_clear => "10",
		lut_preset => "10",
		lut_data => "10",
		TT_size_data => nil_integer_vector,
		Node_Index_data => nil_integer_vector,
		lut_next => "NN00111101001111" &
		            "NN00111101001111",
		pin_names => "GB CLB PRB D QB",
		delay_param =>
			((tpdGB_QB_R, tpdGB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdCLB_QB_R, tpdCLB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdPRB_QB_R, tpdPRB_QB_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_QB_R, tpdD_QB_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		constraint_param => nil_constraint,
		InMapZ => "XXXX",
		Q_feedback => FALSE,
		Enable_feedback => FALSE,
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		Constraint_mesg => FALSE,
		Constraint_xgen => Timing_xgen,
		strn => strn_X01)
	port map(	Input(0) => connect(1),
			Input(1) => connect(3),
			Input(2) => connect(2),
			Input(3) => connect(0),
			Output => QB);


end FTGS;

configuration CFG_LATPC_FTGS of LATPC is
   for FTGS
   end for;
end CFG_LATPC_FTGS;


----- CELL MUX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity MUX2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 690.380 ps;
      tpdA_outb_F                    :	Time := 714.350 ps;
      tpdB_outb_R                    :	Time := 724.830 ps;
      tpdB_outb_F                    :	Time := 735.190 ps;
      tpdSEL_outb_R                  :	Time := 662.750 ps;
      tpdSEL_outb_F                  :	Time := 742.990 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdSEL_R                       :	Time := 0.000 ps;
      twdSEL_F                       :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      SEL                            :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end MUX2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of MUX2 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdSEL_outb_F: constant is 
	"U4/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdSEL_outb_R: constant is 
	"U4/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is 
	"U4/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is 
	"U4/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U4/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U4/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdSEL_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdSEL_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdSEL_R, twdSEL_F, twdSEL_R, twdSEL_R, twdSEL_F, twdSEL_F))
	port map( Input => SEL, Output => connect(2));

   -- Netlist
   U4 : TLU
	generic map(
		N => 3,
		TruthTable => "00100111",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B SEL outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_outb_R, tpdB_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdSEL_outb_R, tpdSEL_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Output => outb);


end FTGS;

configuration CFG_MUX2_FTGS of MUX2 is
   for FTGS
   end for;
end CFG_MUX2_FTGS;


----- CELL NAND2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 170.120 ps;
      tpdA_outb_F                    :	Time := 215.380 ps;
      tpdB_outb_R                    :	Time := 160.430 ps;
      tpdB_outb_F                    :	Time := 205.670 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NAND2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NAND2 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is 
	"U3/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is 
	"U3/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U3/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U3/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   -- Netlist
   U3 : TLU
	generic map(
		N => 2,
		TruthTable => "1110",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_outb_R, tpdB_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Output => outb);


end FTGS;

configuration CFG_NAND2_FTGS of NAND2 is
   for FTGS
   end for;
end CFG_NAND2_FTGS;


----- CELL NAND2C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND2C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 209.250 ps;
      tpdA_out1_F                    :	Time := 291.390 ps;
      tpdB_out1_R                    :	Time := 219.340 ps;
      tpdB_out1_F                    :	Time := 297.390 ps;
      tpdA_out2_R                    :	Time := 534.840 ps;
      tpdA_out2_F                    :	Time := 399.520 ps;
      tpdB_out2_R                    :	Time := 539.370 ps;
      tpdB_out2_F                    :	Time := 410.850 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NAND2C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NAND2C is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is 
	"U4/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is 
	"U4/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is 
	"U4/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is 
	"U4/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is 
	"U3/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is 
	"U3/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is 
	"U3/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is 
	"U3/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   -- Netlist
   U3 : TLU
	generic map(
		N => 2,
		TruthTable => "1110",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B out1",
		delay_param =>
			((tpdA_out1_R, tpdA_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out1_R, tpdB_out1_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Output => out1);

   U4 : TLU
	generic map(
		N => 2,
		TruthTable => "0001",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B out2",
		delay_param =>
			((tpdA_out2_R, tpdA_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out2_R, tpdB_out2_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Output => out2);


end FTGS;

configuration CFG_NAND2C_FTGS of NAND2C is
   for FTGS
   end for;
end CFG_NAND2C_FTGS;


----- CELL NAND3 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND3 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 238.450 ps;
      tpdA_outb_F                    :	Time := 418.700 ps;
      tpdB_outb_R                    :	Time := 238.230 ps;
      tpdB_outb_F                    :	Time := 411.670 ps;
      tpdC_outb_R                    :	Time := 210.960 ps;
      tpdC_outb_F                    :	Time := 391.990 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NAND3;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NAND3 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is 
	"U4/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is 
	"U4/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is 
	"U4/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is 
	"U4/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U4/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U4/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdC_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdC_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdC_R, twdC_F, twdC_R, twdC_R, twdC_F, twdC_F))
	port map( Input => C, Output => connect(2));

   -- Netlist
   U4 : TLU
	generic map(
		N => 3,
		TruthTable => "11111110",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_outb_R, tpdB_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_outb_R, tpdC_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Output => outb);


end FTGS;

configuration CFG_NAND3_FTGS of NAND3 is
   for FTGS
   end for;
end CFG_NAND3_FTGS;


----- CELL NAND3C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND3C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 282.720 ps;
      tpdA_out1_F                    :	Time := 517.310 ps;
      tpdB_out1_R                    :	Time := 268.440 ps;
      tpdB_out1_F                    :	Time := 516.930 ps;
      tpdC_out1_R                    :	Time := 262.570 ps;
      tpdC_out1_F                    :	Time := 497.940 ps;
      tpdA_out2_R                    :	Time := 852.730 ps;
      tpdA_out2_F                    :	Time := 466.010 ps;
      tpdB_out2_R                    :	Time := 808.550 ps;
      tpdB_out2_F                    :	Time := 452.120 ps;
      tpdC_out2_R                    :	Time := 838.570 ps;
      tpdC_out2_F                    :	Time := 482.040 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NAND3C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NAND3C is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdC_out2_F: constant is 
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_out2_R: constant is 
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is 
	"U5/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is 
	"U5/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is 
	"U5/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdC_out1_F: constant is 
	"U4/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_out1_R: constant is 
	"U4/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is 
	"U4/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is 
	"U4/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is 
	"U4/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is 
	"U4/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdC_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdC_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdC_R, twdC_F, twdC_R, twdC_R, twdC_F, twdC_F))
	port map( Input => C, Output => connect(2));

   -- Netlist
   U4 : TLU
	generic map(
		N => 3,
		TruthTable => "11111110",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C out1",
		delay_param =>
			((tpdA_out1_R, tpdA_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out1_R, tpdB_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_out1_R, tpdC_out1_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Output => out1);

   U5 : TLU
	generic map(
		N => 3,
		TruthTable => "00000001",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C out2",
		delay_param =>
			((tpdA_out2_R, tpdA_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out2_R, tpdB_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_out2_R, tpdC_out2_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Output => out2);


end FTGS;

configuration CFG_NAND3C_FTGS of NAND3C is
   for FTGS
   end for;
end CFG_NAND3C_FTGS;


----- CELL NAND4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND4 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 256.650 ps;
      tpdA_outb_F                    :	Time := 564.250 ps;
      tpdB_outb_R                    :	Time := 248.930 ps;
      tpdB_outb_F                    :	Time := 561.040 ps;
      tpdC_outb_R                    :	Time := 227.350 ps;
      tpdC_outb_F                    :	Time := 542.560 ps;
      tpdD_outb_R                    :	Time := 224.720 ps;
      tpdD_outb_F                    :	Time := 510.020 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NAND4;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NAND4 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_outb_F: constant is 
	"U5/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_outb_R: constant is 
	"U5/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is 
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is 
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is 
	"U5/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U5/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U5/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U4/delay(TRAN_10), " &
	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U4/delay(TRAN_01), " &
	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdC_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdC_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdC_R, twdC_F, twdC_R, twdC_R, twdC_F, twdC_F))
	port map( Input => C, Output => connect(2));

   U4 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(3));

   -- Netlist
   U5 : TLU
	generic map(
		N => 4,
		TruthTable => "1111111111111110",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C D outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_outb_R, tpdB_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_outb_R, tpdC_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_outb_R, tpdD_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Input(3) => connect(3), 
		Output => outb);


end FTGS;

configuration CFG_NAND4_FTGS of NAND4 is
   for FTGS
   end for;
end CFG_NAND4_FTGS;


----- CELL NAND4C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND4C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 299.790 ps;
      tpdA_out1_F                    :	Time := 695.020 ps;
      tpdB_out1_R                    :	Time := 290.950 ps;
      tpdB_out1_F                    :	Time := 690.690 ps;
      tpdC_out1_R                    :	Time := 279.570 ps;
      tpdC_out1_F                    :	Time := 670.230 ps;
      tpdD_out1_R                    :	Time := 302.000 ps;
      tpdD_out1_F                    :	Time := 635.750 ps;
      tpdA_out2_R                    :	Time := 1060.930 ps;
      tpdA_out2_F                    :	Time := 486.440 ps;
      tpdB_out2_R                    :	Time := 1055.040 ps;
      tpdB_out2_F                    :	Time := 470.520 ps;
      tpdC_out2_R                    :	Time := 1004.560 ps;
      tpdC_out2_F                    :	Time := 454.790 ps;
      tpdD_out2_R                    :	Time := 976.920 ps;
      tpdD_out2_F                    :	Time := 495.330 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NAND4C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NAND4C is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_out2_F: constant is 
	"U6/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_out2_R: constant is 
	"U6/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdC_out2_F: constant is 
	"U6/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_out2_R: constant is 
	"U6/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is 
	"U6/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is 
	"U6/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is 
	"U6/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is 
	"U6/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdD_out1_F: constant is 
	"U5/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_out1_R: constant is 
	"U5/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdC_out1_F: constant is 
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_out1_R: constant is 
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is 
	"U5/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is 
	"U5/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is 
	"U5/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U4/delay(TRAN_10), " &
	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U4/delay(TRAN_01), " &
	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdC_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdC_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdC_R, twdC_F, twdC_R, twdC_R, twdC_F, twdC_F))
	port map( Input => C, Output => connect(2));

   U4 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(3));

   -- Netlist
   U5 : TLU
	generic map(
		N => 4,
		TruthTable => "1111111111111110",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C D out1",
		delay_param =>
			((tpdA_out1_R, tpdA_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out1_R, tpdB_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_out1_R, tpdC_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_out1_R, tpdD_out1_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Input(3) => connect(3), 
		Output => out1);

   U6 : TLU
	generic map(
		N => 4,
		TruthTable => "0000000000000001",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C D out2",
		delay_param =>
			((tpdA_out2_R, tpdA_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out2_R, tpdB_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_out2_R, tpdC_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_out2_R, tpdD_out2_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Input(3) => connect(3), 
		Output => out2);


end FTGS;

configuration CFG_NAND4C_FTGS of NAND4C is
   for FTGS
   end for;
end CFG_NAND4C_FTGS;


----- CELL NOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 306.120 ps;
      tpdA_outb_F                    :	Time := 180.470 ps;
      tpdB_outb_R                    :	Time := 246.340 ps;
      tpdB_outb_F                    :	Time := 144.220 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NOR2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NOR2 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is 
	"U3/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is 
	"U3/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U3/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U3/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   -- Netlist
   U3 : TLU
	generic map(
		N => 2,
		TruthTable => "1000",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_outb_R, tpdB_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Output => outb);


end FTGS;

configuration CFG_NOR2_FTGS of NOR2 is
   for FTGS
   end for;
end CFG_NOR2_FTGS;


----- CELL NOR2C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR2C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 348.620 ps;
      tpdA_out1_F                    :	Time := 170.630 ps;
      tpdB_out1_R                    :	Time := 419.440 ps;
      tpdB_out1_F                    :	Time := 218.670 ps;
      tpdA_out2_R                    :	Time := 416.760 ps;
      tpdA_out2_F                    :	Time := 550.810 ps;
      tpdB_out2_R                    :	Time := 412.490 ps;
      tpdB_out2_F                    :	Time := 641.700 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NOR2C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NOR2C is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is 
	"U4/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is 
	"U4/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is 
	"U4/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is 
	"U4/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is 
	"U3/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is 
	"U3/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is 
	"U3/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is 
	"U3/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   -- Netlist
   U3 : TLU
	generic map(
		N => 2,
		TruthTable => "1000",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B out1",
		delay_param =>
			((tpdA_out1_R, tpdA_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out1_R, tpdB_out1_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Output => out1);

   U4 : TLU
	generic map(
		N => 2,
		TruthTable => "0111",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B out2",
		delay_param =>
			((tpdA_out2_R, tpdA_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out2_R, tpdB_out2_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Output => out2);


end FTGS;

configuration CFG_NOR2C_FTGS of NOR2C is
   for FTGS
   end for;
end CFG_NOR2C_FTGS;


----- CELL NOR3 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR3 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 638.190 ps;
      tpdA_outb_F                    :	Time := 237.180 ps;
      tpdB_outb_R                    :	Time := 598.690 ps;
      tpdB_outb_F                    :	Time := 221.450 ps;
      tpdC_outb_R                    :	Time := 410.680 ps;
      tpdC_outb_F                    :	Time := 164.140 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NOR3;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NOR3 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is 
	"U4/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is 
	"U4/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is 
	"U4/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is 
	"U4/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U4/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U4/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdC_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdC_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdC_R, twdC_F, twdC_R, twdC_R, twdC_F, twdC_F))
	port map( Input => C, Output => connect(2));

   -- Netlist
   U4 : TLU
	generic map(
		N => 3,
		TruthTable => "10000000",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_outb_R, tpdB_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_outb_R, tpdC_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Output => outb);


end FTGS;

configuration CFG_NOR3_FTGS of NOR3 is
   for FTGS
   end for;
end CFG_NOR3_FTGS;


----- CELL NOR3C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR3C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 827.690 ps;
      tpdA_out1_F                    :	Time := 275.870 ps;
      tpdB_out1_R                    :	Time := 750.880 ps;
      tpdB_out1_F                    :	Time := 258.730 ps;
      tpdC_out1_R                    :	Time := 594.940 ps;
      tpdC_out1_F                    :	Time := 211.280 ps;
      tpdA_out2_R                    :	Time := 507.750 ps;
      tpdA_out2_F                    :	Time := 1086.060 ps;
      tpdB_out2_R                    :	Time := 500.950 ps;
      tpdB_out2_F                    :	Time := 1025.620 ps;
      tpdC_out2_R                    :	Time := 419.950 ps;
      tpdC_out2_F                    :	Time := 861.840 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NOR3C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NOR3C is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdC_out2_F: constant is 
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_out2_R: constant is 
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is 
	"U5/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is 
	"U5/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is 
	"U5/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdC_out1_F: constant is 
	"U4/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_out1_R: constant is 
	"U4/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is 
	"U4/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is 
	"U4/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is 
	"U4/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is 
	"U4/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdC_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdC_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdC_R, twdC_F, twdC_R, twdC_R, twdC_F, twdC_F))
	port map( Input => C, Output => connect(2));

   -- Netlist
   U4 : TLU
	generic map(
		N => 3,
		TruthTable => "10000000",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C out1",
		delay_param =>
			((tpdA_out1_R, tpdA_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out1_R, tpdB_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_out1_R, tpdC_out1_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Output => out1);

   U5 : TLU
	generic map(
		N => 3,
		TruthTable => "01111111",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C out2",
		delay_param =>
			((tpdA_out2_R, tpdA_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out2_R, tpdB_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_out2_R, tpdC_out2_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Output => out2);


end FTGS;

configuration CFG_NOR3C_FTGS of NOR3C is
   for FTGS
   end for;
end CFG_NOR3C_FTGS;


----- CELL NOR4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR4 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 936.830 ps;
      tpdA_outb_F                    :	Time := 227.580 ps;
      tpdB_outb_R                    :	Time := 880.970 ps;
      tpdB_outb_F                    :	Time := 239.880 ps;
      tpdC_outb_R                    :	Time := 730.940 ps;
      tpdC_outb_F                    :	Time := 212.470 ps;
      tpdD_outb_R                    :	Time := 465.420 ps;
      tpdD_outb_F                    :	Time := 169.030 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NOR4;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NOR4 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_outb_F: constant is 
	"U5/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_outb_R: constant is 
	"U5/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is 
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is 
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is 
	"U5/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U5/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U5/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U4/delay(TRAN_10), " &
	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U4/delay(TRAN_01), " &
	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdC_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdC_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdC_R, twdC_F, twdC_R, twdC_R, twdC_F, twdC_F))
	port map( Input => C, Output => connect(2));

   U4 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(3));

   -- Netlist
   U5 : TLU
	generic map(
		N => 4,
		TruthTable => "1000000000000000",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C D outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_outb_R, tpdB_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_outb_R, tpdC_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_outb_R, tpdD_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Input(3) => connect(3), 
		Output => outb);


end FTGS;

configuration CFG_NOR4_FTGS of NOR4 is
   for FTGS
   end for;
end CFG_NOR4_FTGS;


----- CELL NOR4C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR4C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 1075.770 ps;
      tpdA_out1_F                    :	Time := 270.380 ps;
      tpdB_out1_R                    :	Time := 927.680 ps;
      tpdB_out1_F                    :	Time := 250.670 ps;
      tpdC_out1_R                    :	Time := 685.590 ps;
      tpdC_out1_F                    :	Time := 203.320 ps;
      tpdD_out1_R                    :	Time := 1134.410 ps;
      tpdD_out1_F                    :	Time := 269.150 ps;
      tpdA_out2_R                    :	Time := 492.230 ps;
      tpdA_out2_F                    :	Time := 1338.910 ps;
      tpdB_out2_R                    :	Time := 490.670 ps;
      tpdB_out2_F                    :	Time := 1200.570 ps;
      tpdC_out2_R                    :	Time := 421.030 ps;
      tpdC_out2_F                    :	Time := 948.620 ps;
      tpdD_out2_R                    :	Time := 513.930 ps;
      tpdD_out2_F                    :	Time := 1385.250 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NOR4C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of NOR4C is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_out2_F: constant is 
	"U6/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_out2_R: constant is 
	"U6/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdC_out2_F: constant is 
	"U6/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_out2_R: constant is 
	"U6/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is 
	"U6/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is 
	"U6/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is 
	"U6/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is 
	"U6/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdD_out1_F: constant is 
	"U5/delay_param(3)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdD_out1_R: constant is 
	"U5/delay_param(3)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdC_out1_F: constant is 
	"U5/delay_param(2)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdC_out1_R: constant is 
	"U5/delay_param(2)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is 
	"U5/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is 
	"U5/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is 
	"U5/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is 
	"U5/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdD_F: constant is 
	"U4/delay(TRAN_10), " &
	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdD_R: constant is 
	"U4/delay(TRAN_01), " &
	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdC_F: constant is 
	"U3/delay(TRAN_10), " &
	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdC_R: constant is 
	"U3/delay(TRAN_01), " &
	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   U3 : WIREBUF
	generic map(delay => (twdC_R, twdC_F, twdC_R, twdC_R, twdC_F, twdC_F))
	port map( Input => C, Output => connect(2));

   U4 : WIREBUF
	generic map(delay => (twdD_R, twdD_F, twdD_R, twdD_R, twdD_F, twdD_F))
	port map( Input => D, Output => connect(3));

   -- Netlist
   U5 : TLU
	generic map(
		N => 4,
		TruthTable => "1000000000000000",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C D out1",
		delay_param =>
			((tpdA_out1_R, tpdA_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out1_R, tpdB_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_out1_R, tpdC_out1_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_out1_R, tpdD_out1_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Input(3) => connect(3), 
		Output => out1);

   U6 : TLU
	generic map(
		N => 4,
		TruthTable => "0111111111111111",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B C D out2",
		delay_param =>
			((tpdA_out2_R, tpdA_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_out2_R, tpdB_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdC_out2_R, tpdC_out2_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdD_out2_R, tpdD_out2_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "XXXX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Input(2) => connect(2), 
		Input(3) => connect(3), 
		Output => out2);


end FTGS;

configuration CFG_NOR4C_FTGS of NOR4C is
   for FTGS
   end for;
end CFG_NOR4C_FTGS;


----- CELL SINV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity SINV is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 395.840 ps;
      tpdA_outb_F                    :	Time := 350.680 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end SINV;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

architecture FTGS of SINV is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U2/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U2/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";

   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   -- Netlist
   U2 : TLU
	generic map(
		N => 1,
		TruthTable => "10",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A outb",
		delay_param =>
			( 0 => (tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		InMapZ => "X",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Output => outb);


end FTGS;

configuration CFG_SINV_FTGS of SINV is
   for FTGS
   end for;
end CFG_SINV_FTGS;


----- CELL TLU_XNOR2_outb -----
library IEEE;
use IEEE.GS_TYPES.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.strength;

-- entity declaration --
entity TLU_XNOR2_outb is
generic(N: positive := 2;
        TruthTable: val_Z01X_vector;
        TT_size: integer_vector;
        Node_index: integer_vector;
        pin_names: string;
        delay_param: delay_table;
        SDT_values: sdt_values_t;
        InMapZ: val_01X_vector;
        OutMapZ: STD_ULOGIC;
        PulseHandling: PH_OPTION;
        Timing_mesg: BOOLEAN;
        Timing_xgen: BOOLEAN;
        strn: STRENGTH);
port(   Input: in STD_LOGIC_VECTOR(0 to N-1);
        Output: out STD_LOGIC);
end TLU_XNOR2_outb;

-- architecture body --
Library SYNOPSYS;
use SYNOPSYS.attributes.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;
architecture FTGS_SDT of TLU_XNOR2_outb is

function sdt_delay_calc (InStates: STD_LOGIC_VECTOR(0 to 1);
             InEvents: TRANSITION_VECTOR(0 to 1);
             InEventIndex: INTEGER;
             OutEvent: TRANSITION;
             sdt_values: SDT_VALUES_T(0 to 7)) return TIME is

begin
   CASE InEventIndex IS
      WHEN 0 =>
        if    ((InStates(1)='1') and OutEvent=TRAN_01) then
        	return sdt_values(0);
        elsif ((InStates(1)='1') and OutEvent=TRAN_10) then
        	return sdt_values(1);
        elsif ((InStates(1)='0') and OutEvent=TRAN_01) then
        	return sdt_values(2);
        elsif ((InStates(1)='0') and OutEvent=TRAN_10) then
        	return sdt_values(3);
        else return TIME'left;
        end if;
      WHEN 1 =>
        if    ((InStates(0)='1') and OutEvent=TRAN_01) then
        	return sdt_values(4);
        elsif ((InStates(0)='1') and OutEvent=TRAN_10) then
        	return sdt_values(5);
        elsif ((InStates(0)='0') and OutEvent=TRAN_01) then
        	return sdt_values(6);
        elsif ((InStates(0)='0') and OutEvent=TRAN_10) then
        	return sdt_values(7);
        else return TIME'left;
        end if;
      WHEN others =>
         return TIME'left;
   end CASE;
end sdt_delay_calc;

attribute PRIVATE of FTGS_SDT: architecture is TRUE;
attribute SDT_ARCH of FTGS_SDT: architecture is TRUE;
attribute SDT_FUNCTION_FLAG of sdt_delay_calc: function is TRUE;
attribute SDT_FUNCTION of Output: signal is "sdt_delay_calc";

begin
   U1 : TLU
	generic map(
		N => N,
		TruthTable => TruthTable,
		TT_size => TT_size,
		Node_index => Node_index,
		pin_names => pin_names,
		delay_param => delay_param,
		SDT_values => SDT_values,
		InMapZ => InMapZ,
		OutMapZ => OutMapZ,
		PulseHandling => PulseHandling,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn)
	port map(
		Input => Input,
		Output => Output);
end FTGS_SDT;


configuration CFG_TLU_XNOR2_outb_FTGS_SDT of TLU_XNOR2_outb is
   for FTGS_SDT
   end for;
end CFG_TLU_XNOR2_outb_FTGS_SDT;


----- CELL XNOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.GS_TYPES.sdt_values_t;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity XNOR2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 581.840 ps;
      tpdA_outb_F                    :	Time := 523.040 ps;
      tpdB_outb_R                    :	Time := 345.970 ps;
      tpdB_outb_F                    :	Time := 266.650 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      SDT_outb_values : sdt_values_t :=
		(581.84 ps, 523.04 ps, 581.84 ps, 523.04 ps,
		 345.97 ps, 266.65 ps, 345.97 ps, 266.65 ps));

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end XNOR2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;
use SYNOPSYS.attributes.SDT_CONDITION;
use SYNOPSYS.attributes.SDT_VALUE_NAME;
use SYNOPSYS.attributes.SDT_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

library mAMIs050DL;
architecture FTGS of XNOR2 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is 
	"U3/U1/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is 
	"U3/U1/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U3/U1/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U3/U1/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
   attribute SDT_CONDITION of tpdA_outb_R: constant is
   "B==1'B1, B==1'B0";
   attribute SDT_CONDITION of tpdA_outb_F: constant is
   "B==1'B1, B==1'B0";
   attribute SDT_CONDITION of tpdB_outb_R: constant is
   "A==1'B1, A==1'B0";
   attribute SDT_CONDITION of tpdB_outb_F: constant is
   "A==1'B1, A==1'B0";
   attribute SDT_VALUE_NAME of tpdB_outb_F: constant is "U3/U1/SDT_VALUES";
   attribute SDT_VALUE_NAME of tpdB_outb_R: constant is "U3/U1/SDT_VALUES";
   attribute SDT_VALUE_NAME of tpdA_outb_F: constant is "U3/U1/SDT_VALUES";
   attribute SDT_VALUE_NAME of tpdA_outb_R: constant is "U3/U1/SDT_VALUES";
   attribute SDT_VALUE of tpdA_outb_R: constant is "0, 2";
   attribute SDT_VALUE of tpdA_outb_F: constant is "1, 3";
   attribute SDT_VALUE of tpdB_outb_R: constant is "4, 6";
   attribute SDT_VALUE of tpdB_outb_F: constant is "5, 7";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 

   component TLU_XNOR2_outb
   generic(
        N: positive := 2;
        TruthTable: val_Z01X_vector;
        TT_size: integer_vector := nil_integer_vector;
        Node_index: integer_vector := nil_integer_vector;
        pin_names: string;
        delay_param: delay_table;
        SDT_values: sdt_values_t := nil_sdt_values;
        InMapZ: val_01X_vector;
        OutMapZ: STD_ULOGIC;
        PulseHandling: PH_OPTION;
        Timing_mesg: BOOLEAN;
        Timing_xgen: BOOLEAN;
        strn: STRENGTH);
   port(Input: in STD_LOGIC_VECTOR(0 to N-1);
        Output: out STD_LOGIC);
   end component;


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   -- Netlist
   U3 : TLU_XNOR2_outb
	generic map(
		N => 2,
		TruthTable => "1001",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_outb_R, tpdB_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		SDT_values => SDT_outb_values,
		InMapZ => "XX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Output => outb);


end FTGS;

configuration CFG_XNOR2_FTGS of XNOR2 is
   for FTGS
   end for;
end CFG_XNOR2_FTGS;


----- CELL TLU_XOR2_outb -----
library IEEE;
use IEEE.GS_TYPES.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.strength;

-- entity declaration --
entity TLU_XOR2_outb is
generic(N: positive := 2;
        TruthTable: val_Z01X_vector;
        TT_size: integer_vector;
        Node_index: integer_vector;
        pin_names: string;
        delay_param: delay_table;
        SDT_values: sdt_values_t;
        InMapZ: val_01X_vector;
        OutMapZ: STD_ULOGIC;
        PulseHandling: PH_OPTION;
        Timing_mesg: BOOLEAN;
        Timing_xgen: BOOLEAN;
        strn: STRENGTH);
port(   Input: in STD_LOGIC_VECTOR(0 to N-1);
        Output: out STD_LOGIC);
end TLU_XOR2_outb;

-- architecture body --
Library SYNOPSYS;
use SYNOPSYS.attributes.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;
architecture FTGS_SDT of TLU_XOR2_outb is

function sdt_delay_calc (InStates: STD_LOGIC_VECTOR(0 to 1);
             InEvents: TRANSITION_VECTOR(0 to 1);
             InEventIndex: INTEGER;
             OutEvent: TRANSITION;
             sdt_values: SDT_VALUES_T(0 to 7)) return TIME is

begin
   CASE InEventIndex IS
      WHEN 0 =>
        if    ((InStates(1)='1') and OutEvent=TRAN_01) then
        	return sdt_values(0);
        elsif ((InStates(1)='1') and OutEvent=TRAN_10) then
        	return sdt_values(1);
        elsif ((InStates(1)='0') and OutEvent=TRAN_01) then
        	return sdt_values(2);
        elsif ((InStates(1)='0') and OutEvent=TRAN_10) then
        	return sdt_values(3);
        else return TIME'left;
        end if;
      WHEN 1 =>
        if    ((InStates(0)='1') and OutEvent=TRAN_01) then
        	return sdt_values(4);
        elsif ((InStates(0)='1') and OutEvent=TRAN_10) then
        	return sdt_values(5);
        elsif ((InStates(0)='0') and OutEvent=TRAN_01) then
        	return sdt_values(6);
        elsif ((InStates(0)='0') and OutEvent=TRAN_10) then
        	return sdt_values(7);
        else return TIME'left;
        end if;
      WHEN others =>
         return TIME'left;
   end CASE;
end sdt_delay_calc;

attribute PRIVATE of FTGS_SDT: architecture is TRUE;
attribute SDT_ARCH of FTGS_SDT: architecture is TRUE;
attribute SDT_FUNCTION_FLAG of sdt_delay_calc: function is TRUE;
attribute SDT_FUNCTION of Output: signal is "sdt_delay_calc";

begin
   U1 : TLU
	generic map(
		N => N,
		TruthTable => TruthTable,
		TT_size => TT_size,
		Node_index => Node_index,
		pin_names => pin_names,
		delay_param => delay_param,
		SDT_values => SDT_values,
		InMapZ => InMapZ,
		OutMapZ => OutMapZ,
		PulseHandling => PulseHandling,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn)
	port map(
		Input => Input,
		Output => Output);
end FTGS_SDT;


configuration CFG_TLU_XOR2_outb_FTGS_SDT of TLU_XOR2_outb is
   for FTGS_SDT
   end for;
end CFG_TLU_XOR2_outb_FTGS_SDT;


----- CELL XOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.GS_TYPES.sdt_values_t;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity XOR2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 353.260 ps;
      tpdA_outb_F                    :	Time := 325.270 ps;
      tpdB_outb_R                    :	Time := 563.810 ps;
      tpdB_outb_F                    :	Time := 785.000 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      SDT_outb_values : sdt_values_t :=
		(353.26 ps, 325.27 ps, 353.26 ps, 325.27 ps,
		 563.81 ps, 785.00 ps, 563.81 ps, 785.00 ps));

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end XOR2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;
use SYNOPSYS.attributes.SDT_CONDITION;
use SYNOPSYS.attributes.SDT_VALUE_NAME;
use SYNOPSYS.attributes.SDT_VALUE;

library IEEE;
use IEEE.GS_TYPES.all;
library GSCOMP;
use GSCOMP.GS_COMPONENTS.all;

library mAMIs050DL;
architecture FTGS of XOR2 is
   attribute PRIVATE of FTGS : architecture is TRUE;
   attribute ASIC_CELL of FTGS : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is 
	"U3/U1/delay_param(1)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is 
	"U3/U1/delay_param(1)(TRAN_01)";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is 
	"U3/U1/delay_param(0)(TRAN_10)";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is 
	"U3/U1/delay_param(0)(TRAN_01)";
   attribute PROPAGATE_VALUE of twdB_F: constant is 
	"U2/delay(TRAN_10), " &
	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdB_R: constant is 
	"U2/delay(TRAN_01), " &
	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
   attribute PROPAGATE_VALUE of twdA_F: constant is 
	"U1/delay(TRAN_10), " &
	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
   attribute PROPAGATE_VALUE of twdA_R: constant is 
	"U1/delay(TRAN_01), " &
	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
   attribute SDT_CONDITION of tpdA_outb_R: constant is
   "B==1'B1, B==1'B0";
   attribute SDT_CONDITION of tpdA_outb_F: constant is
   "B==1'B1, B==1'B0";
   attribute SDT_CONDITION of tpdB_outb_R: constant is
   "A==1'B1, A==1'B0";
   attribute SDT_CONDITION of tpdB_outb_F: constant is
   "A==1'B1, A==1'B0";
   attribute SDT_VALUE_NAME of tpdB_outb_F: constant is "U3/U1/SDT_VALUES";
   attribute SDT_VALUE_NAME of tpdB_outb_R: constant is "U3/U1/SDT_VALUES";
   attribute SDT_VALUE_NAME of tpdA_outb_F: constant is "U3/U1/SDT_VALUES";
   attribute SDT_VALUE_NAME of tpdA_outb_R: constant is "U3/U1/SDT_VALUES";
   attribute SDT_VALUE of tpdA_outb_R: constant is "0, 2";
   attribute SDT_VALUE of tpdA_outb_F: constant is "1, 3";
   attribute SDT_VALUE of tpdB_outb_R: constant is "4, 6";
   attribute SDT_VALUE of tpdB_outb_F: constant is "5, 7";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 

   component TLU_XOR2_outb
   generic(
        N: positive := 2;
        TruthTable: val_Z01X_vector;
        TT_size: integer_vector := nil_integer_vector;
        Node_index: integer_vector := nil_integer_vector;
        pin_names: string;
        delay_param: delay_table;
        SDT_values: sdt_values_t := nil_sdt_values;
        InMapZ: val_01X_vector;
        OutMapZ: STD_ULOGIC;
        PulseHandling: PH_OPTION;
        Timing_mesg: BOOLEAN;
        Timing_xgen: BOOLEAN;
        strn: STRENGTH);
   port(Input: in STD_LOGIC_VECTOR(0 to N-1);
        Output: out STD_LOGIC);
   end component;


begin

   -- Extrinsic delay buffers
   U1 : WIREBUF
	generic map(delay => (twdA_R, twdA_F, twdA_R, twdA_R, twdA_F, twdA_F))
	port map( Input => A, Output => connect(0));

   U2 : WIREBUF
	generic map(delay => (twdB_R, twdB_F, twdB_R, twdB_R, twdB_F, twdB_F))
	port map( Input => B, Output => connect(1));

   -- Netlist
   U3 : TLU_XOR2_outb
	generic map(
		N => 2,
		TruthTable => "0110",
		TT_size => nil_integer_vector,
		Node_index => nil_integer_vector,
		pin_names => "A B outb",
		delay_param =>
			((tpdA_outb_R, tpdA_outb_F, 0 ps, 0 ps, 0 ps, 0 ps),
			 (tpdB_outb_R, tpdB_outb_F, 0 ps, 0 ps, 0 ps, 0 ps)),
		SDT_values => SDT_outb_values,
		InMapZ => "XX",
		OutMapZ => 'Z',
		PulseHandling => PH_GLITCH,
		Timing_mesg => Timing_mesg,
		Timing_xgen => Timing_xgen,
		strn => strn_X01)
	port map(
		Input(0) => connect(0), 
		Input(1) => connect(1), 
		Output => outb);


end FTGS;

configuration CFG_XOR2_FTGS of XOR2 is
   for FTGS
   end for;
end CFG_XOR2_FTGS;


---- end of library ----
