Update History
MOSIS AMI 0.5um - Submicron Rules
SCMOSLib Digital Standard Cell Library
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31Oct2001
- Updated transistor sizes in layout and schematic for matching: DFFC, DFFP, DFFPC, BUFZ, NAND4C and SINVZ

08Oct2001
- Updated Technology name to SCN3ME_SUBM, was SCN3M_SUBM.
- Updated all large metal rules to ignore most conditions in DRC setup.

31Jul2001
- Update to current Mosis AMI C5N SCN3ME 

12July2000
-Replaced setup from PadLib to be consistent.

11July2000
- Change name from PadFC to PadlessCorner.
- SPR Pad Route Setup: Layers tab, changed Pad via layer to Via1

31Jan2000
- Added rule 27.6b
- Removed NW/Poly resistor

17Jan2000
-mAMIs05.tdb, mAMIs05DL.tdb: updated poly2 wire to include: not "High Res Implant"

05Oct99
-mAMIs05DL.tdb: Match abut to origin
		Fixed DRC errors for ports and standard cells
		DRC rules 8.5 (a,b,c,d) are disabled
		DRC rules 9.2 (b,c) are disabled
-mAMIs05.ext:	Add statement for poly resistor over Nwell

Initial Released 03SEP99
- MOSIS TSMC 0.5um Design Kit
  Technology = SCN3M_SUBM lambda = 0.30um

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Copyright (c) 2000-2001 Tanner Research, Inc.  All rights reserved.

Tanner Research, Inc.
2650 East Foothill Blvd.
Pasadena, CA  91107 USA

Telephone: (626) 792-3000
Fax:       (626) 792-0300
e-mail:    ces@tanner.com
