
----------------------------------------------------------------
-- 
-- Created by the Synopsys Library Compiler 1999.10
-- FILENAME     :    mAMIs050DL_components.vhd
-- FILE CONTENTS:    Component Package
-- DATE CREATED :    Thu Jun 15 18:02:53 2000
-- 
-- LIBRARY      :    mAMIs050DL
-- REVISION     :    Not Specified
-- TECHNOLOGY   :    cmos
-- TIME SCALE   :    1 ps
-- LOGIC SYSTEM :    IEEE-1164
-- NOTES        :    
-- HISTORY      :
-- 
----------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off
use IEEE.GS_TYPES.sdt_values_t;
-- synopsys translate_on

package COMPONENTS is

constant Default_Timing_mesg : Boolean := True;
constant Default_Timing_xgen : Boolean := False;

----- Component AO22 -----
component AO22
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 879.730 ps;
      tpdA_outb_F                    :	Time := 716.920 ps;
      tpdB_outb_R                    :	Time := 940.160 ps;
      tpdB_outb_F                    :	Time := 729.560 ps;
      tpdC_outb_R                    :	Time := 640.380 ps;
      tpdC_outb_F                    :	Time := 534.000 ps;
      tpdD_outb_R                    :	Time := 622.660 ps;
      tpdD_outb_F                    :	Time := 551.380 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component AOI22 -----
component AOI22
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 424.960 ps;
      tpdA_outb_F                    :	Time := 485.330 ps;
      tpdB_outb_R                    :	Time := 413.220 ps;
      tpdB_outb_F                    :	Time := 479.170 ps;
      tpdC_outb_R                    :	Time := 218.800 ps;
      tpdC_outb_F                    :	Time := 236.940 ps;
      tpdD_outb_R                    :	Time := 233.150 ps;
      tpdD_outb_F                    :	Time := 246.650 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component BUF1 -----
component BUF1
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 336.960 ps;
      tpdA_outb_F                    :	Time := 352.160 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component BUF4 -----
component BUF4
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 427.380 ps;
      tpdA_outb_F                    :	Time := 517.550 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component BUFI4 -----
component BUFI4
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 88.510 ps;
      tpdA_outb_F                    :	Time := 88.290 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component BUFZ -----
component BUFZ
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 833.610 ps;
      tpdA_outb_F                    :	Time := 752.680 ps;
      tpdOEB_outb_R                  :	Time := 291.490 ps;
      tpdOEB_outb_F                  :	Time := 193.780 ps;
      tpdOEB_outb_LZ                 :	Time := 291.490 ps;
      tpdOEB_outb_HZ                 :	Time := 193.780 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdOEB_R                       :	Time := 0.000 ps;
      twdOEB_F                       :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      OEB                            :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component DFF -----
component DFF
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdCLK_Q_R                     :	Time := 1763.660 ps;
      tpdCLK_Q_F                     :	Time := 1535.840 ps;
      tpdCLK_QB_R                    :	Time := 1293.840 ps;
      tpdCLK_QB_F                    :	Time := 1513.420 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 450.000 ps;
      twCLK_H                        :	Time := 750.000 ps;
      twCLK_L                        :	Time := 750.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end component;


----- Component DFFC -----
component DFFC
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdCLB_Q_F                     :	Time := 590.630 ps;
      tpdCLK_Q_R                     :	Time := 2426.230 ps;
      tpdCLK_Q_F                     :	Time := 1898.930 ps;
      tpdCLB_QB_R                    :	Time := 100.000 ps;
      tpdCLB_QB_F                    :	Time := 2272.700 ps;
      tpdCLK_QB_R                    :	Time := 1424.740 ps;
      tpdCLK_QB_F                    :	Time := 1736.000 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 560.000 ps;
      twCLK_H                        :	Time := 980.000 ps;
      twCLK_L                        :	Time := 980.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end component;


----- Component DFFP -----
component DFFP
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdPRB_Q_R                     :	Time := 806.750 ps;
      tpdCLK_Q_R                     :	Time := 1984.310 ps;
      tpdCLK_Q_F                     :	Time := 1904.280 ps;
      tpdPRB_QB_F                    :	Time := 477.540 ps;
      tpdCLK_QB_R                    :	Time := 1542.680 ps;
      tpdCLK_QB_F                    :	Time := 1658.400 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 460.000 ps;
      twCLK_H                        :	Time := 880.000 ps;
      twCLK_L                        :	Time := 880.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end component;


----- Component DFFPC -----
component DFFPC
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdPRB_Q_R                     :	Time := 1152.300 ps;
      tpdCLB_Q_F                     :	Time := 514.590 ps;
      tpdCLK_Q_R                     :	Time := 2547.160 ps;
      tpdCLK_Q_F                     :	Time := 2043.240 ps;
      tpdPRB_QB_F                    :	Time := 419.190 ps;
      tpdCLB_QB_R                    :	Time := 1587.030 ps;
      tpdCLK_QB_R                    :	Time := 1556.220 ps;
      tpdCLK_QB_F                    :	Time := 1901.760 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 512.970 ps;
      twCLK_H                        :	Time := 1050.000 ps;
      twCLK_L                        :	Time := 1050.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end component;


----- Component INV -----
component INV
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 147.050 ps;
      tpdA_outb_F                    :	Time := 131.020 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component INV2 -----
component INV2
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_out1_R                    :	Time := 143.010 ps;
      tpdA_out1_F                    :	Time := 133.030 ps;
      tpdB_out2_R                    :	Time := 142.700 ps;
      tpdB_out2_F                    :	Time := 132.800 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end component;


----- Component INVZ -----
component INVZ
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdOEB_outb_R                  :	Time := 0.000 ps;
      tpdOEB_outb_F                  :	Time := 172.430 ps;
      tpdOEB_outb_LZ                 :	Time := 0.000 ps;
      tpdOEB_outb_HZ                 :	Time := 172.430 ps;
      tpdA_outb_R                    :	Time := 204.660 ps;
      tpdA_outb_F                    :	Time := 191.380 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdOEB_R                       :	Time := 0.000 ps;
      twdOEB_F                       :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      OEB                            :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component LAT -----
component LAT
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdD_Q_R                       :	Time := 747.850 ps;
      tpdD_Q_F                       :	Time := 775.010 ps;
      tpdGB_Q_R                      :	Time := 1219.200 ps;
      tpdGB_Q_F                      :	Time := 1031.260 ps;
      tpdD_QB_R                      :	Time := 1019.590 ps;
      tpdD_QB_F                      :	Time := 950.320 ps;
      tpdGB_QB_R                     :	Time := 1434.270 ps;
      tpdGB_QB_F                     :	Time := 1227.970 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end component;


----- Component LATC -----
component LATC
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdD_Q_R                       :	Time := 1284.890 ps;
      tpdD_Q_F                       :	Time := 1170.820 ps;
      tpdGB_Q_R                      :	Time := 1222.430 ps;
      tpdGB_Q_F                      :	Time := 1585.660 ps;
      tpdCLB_Q_F                     :	Time := 390.060 ps;
      tpdD_QB_R                      :	Time := 976.820 ps;
      tpdD_QB_F                      :	Time := 1002.540 ps;
      tpdGB_QB_R                     :	Time := 1032.910 ps;
      tpdGB_QB_F                     :	Time := 1297.520 ps;
      tpdCLB_QB_F                    :	Time := 201.080 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end component;


----- Component LATP -----
component LATP
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdD_Q_R                       :	Time := 776.950 ps;
      tpdD_Q_F                       :	Time := 850.480 ps;
      tpdGB_Q_R                      :	Time := 1277.980 ps;
      tpdGB_Q_F                      :	Time := 1063.400 ps;
      tpdPRB_Q_R                     :	Time := 196.360 ps;
      tpdD_QB_R                      :	Time := 1145.520 ps;
      tpdD_QB_F                      :	Time := 980.720 ps;
      tpdGB_QB_R                     :	Time := 1517.700 ps;
      tpdGB_QB_F                     :	Time := 1247.490 ps;
      tpdPRB_QB_R                    :	Time := 100.000 ps;
      tpdPRB_QB_F                    :	Time := 388.620 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end component;


----- Component LATPC -----
component LATPC
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdD_Q_R                       :	Time := 961.030 ps;
      tpdD_Q_F                       :	Time := 954.510 ps;
      tpdGB_Q_R                      :	Time := 1399.670 ps;
      tpdGB_Q_F                      :	Time := 1244.420 ps;
      tpdPRB_Q_R                     :	Time := 279.160 ps;
      tpdCLB_Q_F                     :	Time := 625.340 ps;
      tpdD_QB_R                      :	Time := 1264.200 ps;
      tpdD_QB_F                      :	Time := 1219.990 ps;
      tpdGB_QB_R                     :	Time := 1687.280 ps;
      tpdGB_QB_F                     :	Time := 1484.680 ps;
      tpdPRB_QB_R                    :	Time := 100.000 ps;
      tpdPRB_QB_F                    :	Time := 489.970 ps;
      tpdCLB_QB_R                    :	Time := 907.590 ps;
      tpdCLB_QB_F                    :	Time := 100.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end component;


----- Component MUX2 -----
component MUX2
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 690.380 ps;
      tpdA_outb_F                    :	Time := 714.350 ps;
      tpdB_outb_R                    :	Time := 724.830 ps;
      tpdB_outb_F                    :	Time := 735.190 ps;
      tpdSEL_outb_R                  :	Time := 662.750 ps;
      tpdSEL_outb_F                  :	Time := 742.990 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdSEL_R                       :	Time := 0.000 ps;
      twdSEL_F                       :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      SEL                            :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component NAND2 -----
component NAND2
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 170.120 ps;
      tpdA_outb_F                    :	Time := 215.380 ps;
      tpdB_outb_R                    :	Time := 160.430 ps;
      tpdB_outb_F                    :	Time := 205.670 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component NAND2C -----
component NAND2C
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_out1_R                    :	Time := 209.250 ps;
      tpdA_out1_F                    :	Time := 291.390 ps;
      tpdB_out1_R                    :	Time := 219.340 ps;
      tpdB_out1_F                    :	Time := 297.390 ps;
      tpdA_out2_R                    :	Time := 534.840 ps;
      tpdA_out2_F                    :	Time := 399.520 ps;
      tpdB_out2_R                    :	Time := 539.370 ps;
      tpdB_out2_F                    :	Time := 410.850 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end component;


----- Component NAND3 -----
component NAND3
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 238.450 ps;
      tpdA_outb_F                    :	Time := 418.700 ps;
      tpdB_outb_R                    :	Time := 238.230 ps;
      tpdB_outb_F                    :	Time := 411.670 ps;
      tpdC_outb_R                    :	Time := 210.960 ps;
      tpdC_outb_F                    :	Time := 391.990 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component NAND3C -----
component NAND3C
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_out1_R                    :	Time := 282.720 ps;
      tpdA_out1_F                    :	Time := 517.310 ps;
      tpdB_out1_R                    :	Time := 268.440 ps;
      tpdB_out1_F                    :	Time := 516.930 ps;
      tpdC_out1_R                    :	Time := 262.570 ps;
      tpdC_out1_F                    :	Time := 497.940 ps;
      tpdA_out2_R                    :	Time := 852.730 ps;
      tpdA_out2_F                    :	Time := 466.010 ps;
      tpdB_out2_R                    :	Time := 808.550 ps;
      tpdB_out2_F                    :	Time := 452.120 ps;
      tpdC_out2_R                    :	Time := 838.570 ps;
      tpdC_out2_F                    :	Time := 482.040 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end component;


----- Component NAND4 -----
component NAND4
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 256.650 ps;
      tpdA_outb_F                    :	Time := 564.250 ps;
      tpdB_outb_R                    :	Time := 248.930 ps;
      tpdB_outb_F                    :	Time := 561.040 ps;
      tpdC_outb_R                    :	Time := 227.350 ps;
      tpdC_outb_F                    :	Time := 542.560 ps;
      tpdD_outb_R                    :	Time := 224.720 ps;
      tpdD_outb_F                    :	Time := 510.020 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component NAND4C -----
component NAND4C
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_out1_R                    :	Time := 299.790 ps;
      tpdA_out1_F                    :	Time := 695.020 ps;
      tpdB_out1_R                    :	Time := 290.950 ps;
      tpdB_out1_F                    :	Time := 690.690 ps;
      tpdC_out1_R                    :	Time := 279.570 ps;
      tpdC_out1_F                    :	Time := 670.230 ps;
      tpdD_out1_R                    :	Time := 302.000 ps;
      tpdD_out1_F                    :	Time := 635.750 ps;
      tpdA_out2_R                    :	Time := 1060.930 ps;
      tpdA_out2_F                    :	Time := 486.440 ps;
      tpdB_out2_R                    :	Time := 1055.040 ps;
      tpdB_out2_F                    :	Time := 470.520 ps;
      tpdC_out2_R                    :	Time := 1004.560 ps;
      tpdC_out2_F                    :	Time := 454.790 ps;
      tpdD_out2_R                    :	Time := 976.920 ps;
      tpdD_out2_F                    :	Time := 495.330 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end component;


----- Component NOR2 -----
component NOR2
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 306.120 ps;
      tpdA_outb_F                    :	Time := 180.470 ps;
      tpdB_outb_R                    :	Time := 246.340 ps;
      tpdB_outb_F                    :	Time := 144.220 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component NOR2C -----
component NOR2C
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_out1_R                    :	Time := 348.620 ps;
      tpdA_out1_F                    :	Time := 170.630 ps;
      tpdB_out1_R                    :	Time := 419.440 ps;
      tpdB_out1_F                    :	Time := 218.670 ps;
      tpdA_out2_R                    :	Time := 416.760 ps;
      tpdA_out2_F                    :	Time := 550.810 ps;
      tpdB_out2_R                    :	Time := 412.490 ps;
      tpdB_out2_F                    :	Time := 641.700 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end component;


----- Component NOR3 -----
component NOR3
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 638.190 ps;
      tpdA_outb_F                    :	Time := 237.180 ps;
      tpdB_outb_R                    :	Time := 598.690 ps;
      tpdB_outb_F                    :	Time := 221.450 ps;
      tpdC_outb_R                    :	Time := 410.680 ps;
      tpdC_outb_F                    :	Time := 164.140 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component NOR3C -----
component NOR3C
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_out1_R                    :	Time := 827.690 ps;
      tpdA_out1_F                    :	Time := 275.870 ps;
      tpdB_out1_R                    :	Time := 750.880 ps;
      tpdB_out1_F                    :	Time := 258.730 ps;
      tpdC_out1_R                    :	Time := 594.940 ps;
      tpdC_out1_F                    :	Time := 211.280 ps;
      tpdA_out2_R                    :	Time := 507.750 ps;
      tpdA_out2_F                    :	Time := 1086.060 ps;
      tpdB_out2_R                    :	Time := 500.950 ps;
      tpdB_out2_F                    :	Time := 1025.620 ps;
      tpdC_out2_R                    :	Time := 419.950 ps;
      tpdC_out2_F                    :	Time := 861.840 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end component;


----- Component NOR4 -----
component NOR4
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 936.830 ps;
      tpdA_outb_F                    :	Time := 227.580 ps;
      tpdB_outb_R                    :	Time := 880.970 ps;
      tpdB_outb_F                    :	Time := 239.880 ps;
      tpdC_outb_R                    :	Time := 730.940 ps;
      tpdC_outb_F                    :	Time := 212.470 ps;
      tpdD_outb_R                    :	Time := 465.420 ps;
      tpdD_outb_F                    :	Time := 169.030 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component NOR4C -----
component NOR4C
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_out1_R                    :	Time := 1075.770 ps;
      tpdA_out1_F                    :	Time := 270.380 ps;
      tpdB_out1_R                    :	Time := 927.680 ps;
      tpdB_out1_F                    :	Time := 250.670 ps;
      tpdC_out1_R                    :	Time := 685.590 ps;
      tpdC_out1_F                    :	Time := 203.320 ps;
      tpdD_out1_R                    :	Time := 1134.410 ps;
      tpdD_out1_F                    :	Time := 269.150 ps;
      tpdA_out2_R                    :	Time := 492.230 ps;
      tpdA_out2_F                    :	Time := 1338.910 ps;
      tpdB_out2_R                    :	Time := 490.670 ps;
      tpdB_out2_F                    :	Time := 1200.570 ps;
      tpdC_out2_R                    :	Time := 421.030 ps;
      tpdC_out2_F                    :	Time := 948.620 ps;
      tpdD_out2_R                    :	Time := 513.930 ps;
      tpdD_out2_F                    :	Time := 1385.250 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end component;


----- Component SINV -----
component SINV
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 395.840 ps;
      tpdA_outb_F                    :	Time := 350.680 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component XNOR2 -----
component XNOR2
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 581.840 ps;
      tpdA_outb_F                    :	Time := 523.040 ps;
      tpdB_outb_R                    :	Time := 345.970 ps;
      tpdB_outb_F                    :	Time := 266.650 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      SDT_outb_values : sdt_values_t :=
		(581.84 ps, 523.04 ps, 581.84 ps, 523.04 ps,
		 345.97 ps, 266.65 ps, 345.97 ps, 266.65 ps));

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


----- Component XOR2 -----
component XOR2
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_outb_R                    :	Time := 353.260 ps;
      tpdA_outb_F                    :	Time := 325.270 ps;
      tpdB_outb_R                    :	Time := 563.810 ps;
      tpdB_outb_F                    :	Time := 785.000 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      SDT_outb_values : sdt_values_t :=
		(353.26 ps, 325.27 ps, 353.26 ps, 325.27 ps,
		 563.81 ps, 785.00 ps, 563.81 ps, 785.00 ps));

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);
end component;


end COMPONENTS;

---- end of components library ----
