
----------------------------------------------------------------
-- 
-- Created by the Synopsys Library Compiler 1999.10
-- FILENAME     :    mAMIs050DL_FTSM.vhd
-- FILE CONTENTS:    Entity, Structural Architecture(FTSM),
--                   and Configuration
-- DATE CREATED :    Thu Jun 15 18:02:53 2000
-- 
-- LIBRARY      :    mAMIs050DL
-- REVISION     :    Not Specified
-- TECHNOLOGY   :    cmos
-- TIME SCALE   :    1 ps
-- LOGIC SYSTEM :    IEEE-1164
-- NOTES        :    FTSM, Timing_mesg(TRUE)
-- HISTORY      :
-- 
----------------------------------------------------------------

----- CELL AO22 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity AO22 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 879.730 ps;
      tpdA_outb_F                    :	Time := 716.920 ps;
      tpdB_outb_R                    :	Time := 940.160 ps;
      tpdB_outb_F                    :	Time := 729.560 ps;
      tpdC_outb_R                    :	Time := 640.380 ps;
      tpdC_outb_F                    :	Time := 534.000 ps;
      tpdD_outb_R                    :	Time := 622.660 ps;
      tpdD_outb_F                    :	Time := 551.380 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end AO22;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of AO22 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_outb_R: constant is "U8/tLH";
   attribute PROPAGATE_VALUE of tpdD_outb_F: constant is "U8/tHL";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is "U7/tLH";
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is "U7/tHL";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of twdC_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdC_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal n1, n2 : STD_LOGIC;

   component NAND2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdC_R, tHL => twdC_F)
	port map( Input => C, Output => connect(2));

   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(3));

   -- Intrinsic delay buffers
   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_R, tHL => tpdA_outb_F)
	port map( Input => connect(0), Output => prop_outb(0));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_outb_R, tHL => tpdB_outb_F)
	port map( Input => connect(1), Output => prop_outb(1));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_outb_R, tHL => tpdC_outb_F)
	port map( Input => connect(2), Output => prop_outb(2));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_outb_R, tHL => tpdD_outb_F)
	port map( Input => connect(3), Output => prop_outb(3));

   -- Netlist
   U9 : NAND2MAC
	port map( I0 => n1, I1 => n2, Y => outb);

   U10 : NAND2MAC
	port map( I0 => prop_outb(2), I1 => prop_outb(3), Y => n2);

   U11 : NAND2MAC
	port map( I0 => prop_outb(0), I1 => prop_outb(1), Y => n1);


end FTSM;

configuration CFG_AO22_FTSM of AO22 is
   for FTSM
   end for;
end CFG_AO22_FTSM;


----- CELL AOI22 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity AOI22 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 424.960 ps;
      tpdA_outb_F                    :	Time := 485.330 ps;
      tpdB_outb_R                    :	Time := 413.220 ps;
      tpdB_outb_F                    :	Time := 479.170 ps;
      tpdC_outb_R                    :	Time := 218.800 ps;
      tpdC_outb_F                    :	Time := 236.940 ps;
      tpdD_outb_R                    :	Time := 233.150 ps;
      tpdD_outb_F                    :	Time := 246.650 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end AOI22;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of AOI22 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_outb_F: constant is "U8/tLH";
   attribute PROPAGATE_VALUE of tpdD_outb_R: constant is "U8/tHL";
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is "U7/tLH";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is "U7/tHL";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of twdC_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdC_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal n1, n2 : STD_LOGIC;

   component AND2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

   component NAND2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdC_R, tHL => twdC_F)
	port map( Input => C, Output => connect(2));

   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(3));

   -- Intrinsic delay buffers
   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_F, tHL => tpdA_outb_R)
	port map( Input => connect(0), Output => prop_outb(0));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_outb_F, tHL => tpdB_outb_R)
	port map( Input => connect(1), Output => prop_outb(1));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_outb_F, tHL => tpdC_outb_R)
	port map( Input => connect(2), Output => prop_outb(2));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_outb_F, tHL => tpdD_outb_R)
	port map( Input => connect(3), Output => prop_outb(3));

   -- Netlist
   U9 : AND2MAC
	port map( I0 => n1, I1 => n2, Y => outb);

   U10 : NAND2MAC
	port map( I0 => prop_outb(2), I1 => prop_outb(3), Y => n2);

   U11 : NAND2MAC
	port map( I0 => prop_outb(0), I1 => prop_outb(1), Y => n1);


end FTSM;

configuration CFG_AOI22_FTSM of AOI22 is
   for FTSM
   end for;
end CFG_AOI22_FTSM;


----- CELL BUF1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity BUF1 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 336.960 ps;
      tpdA_outb_F                    :	Time := 352.160 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end BUF1;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of BUF1 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   -- Concurrent assignments
   U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_R, tHL => tpdA_outb_F)
	port map( Input => connect(0), Output => outb);


end FTSM;

configuration CFG_BUF1_FTSM of BUF1 is
   for FTSM
   end for;
end CFG_BUF1_FTSM;


----- CELL BUF4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity BUF4 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 427.380 ps;
      tpdA_outb_F                    :	Time := 517.550 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end BUF4;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of BUF4 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   -- Concurrent assignments
   U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_R, tHL => tpdA_outb_F)
	port map( Input => connect(0), Output => outb);


end FTSM;

configuration CFG_BUF4_FTSM of BUF4 is
   for FTSM
   end for;
end CFG_BUF4_FTSM;


----- CELL BUFI4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity BUFI4 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 88.510 ps;
      tpdA_outb_F                    :	Time := 88.290 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end BUFI4;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of BUFI4 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U2/U1/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U2/U1/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');

   component INVMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   -- Netlist
   U2 : INVMAC
	generic map( tpdY_R => tpdA_outb_R, tpdY_F => tpdA_outb_F )
	port map( I0 => connect(0), Y => outb);


end FTSM;

configuration CFG_BUFI4_FTSM of BUFI4 is
   for FTSM
   end for;
end CFG_BUFI4_FTSM;


----- CELL BUFZ -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity BUFZ is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 833.610 ps;
      tpdA_outb_F                    :	Time := 752.680 ps;
      tpdOEB_outb_R                  :	Time := 291.490 ps;
      tpdOEB_outb_F                  :	Time := 193.780 ps;
      tpdOEB_outb_LZ                 :	Time := 291.490 ps;
      tpdOEB_outb_HZ                 :	Time := 193.780 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdOEB_R                       :	Time := 0.000 ps;
      twdOEB_F                       :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      OEB                            :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end BUFZ;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of BUFZ is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdOEB_outb_R: constant is "U4/tHL, U4/tLH";
   attribute PROPAGATE_VALUE of tpdOEB_outb_HZ: constant is "U4/tLH, U4/tHL";
   attribute PROPAGATE_VALUE of tpdOEB_outb_LZ: constant is "U4/tLH, U4/tHL";
   attribute PROPAGATE_VALUE of tpdOEB_outb_F: constant is "U4/tLH, U4/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdOEB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdOEB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');

   component BUF3SLEMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         OEN                            :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdOEB_R, tHL => twdOEB_F)
	port map( Input => OEB, Output => connect(1));

   -- Intrinsic delay buffers
   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_R, tHL => tpdA_outb_F)
	port map( Input => connect(0), Output => prop_outb(0));

   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdOEB_outb_R, tHL => tpdOEB_outb_R)
	port map( Input => connect(1), Output => prop_outb(1));

   -- Netlist
   U5 : BUF3SLEMAC
	port map( I0 => prop_outb(0), OEN => prop_outb(1), Y => outb);


end FTSM;

configuration CFG_BUFZ_FTSM of BUFZ is
   for FTSM
   end for;
end CFG_BUFZ_FTSM;


----- CELL DFF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity DFF is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdCLK_Q_R                     :	Time := 1763.660 ps;
      tpdCLK_Q_F                     :	Time := 1535.840 ps;
      tpdCLK_QB_R                    :	Time := 1293.840 ps;
      tpdCLK_QB_F                    :	Time := 1513.420 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 450.000 ps;
      twCLK_H                        :	Time := 750.000 ps;
      twCLK_L                        :	Time := 750.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end DFF;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of DFF is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tsuD_CLK: constant is "FEC/F3/tSetup";
   attribute PROPAGATE_VALUE of thCLK_D: constant is "FEC/F2/tHold";
   attribute PROPAGATE_VALUE of twCLK_L: constant is "FEC/F1/tLow";
   attribute PROPAGATE_VALUE of twCLK_H: constant is "FEC/F1/tHigh";
   attribute PROPAGATE_VALUE of tpdCLK_QB_F: constant is "U4/U1/tHL";
   attribute PROPAGATE_VALUE of tpdCLK_QB_R: constant is "U4/U1/tLH";
   attribute PROPAGATE_VALUE of tpdCLK_Q_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of tpdCLK_Q_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdCLK_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdCLK_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal Q_net2_1, n1 : STD_LOGIC;

   component INVMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

   component DFFLMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         D                              :  in    STD_LOGIC;
         CLK                            :  in    STD_LOGIC;
         CLR                            :  in    STD_LOGIC;
         Q                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdCLK_R, tHL => twdCLK_F)
	port map( Input => CLK, Output => connect(1));

   -- Concurrent assignments
   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_Q_R, tHL => tpdCLK_Q_F)
	port map( Input => Q_net2_1, Output => Q);

   -- Netlist
   U4 : INVMAC
	generic map( tpdY_R => tpdCLK_QB_R, tpdY_F => tpdCLK_QB_F )
	port map( I0 => Q_net2_1, Y => QB);

   U5 : DFFLMAC
	port map( D => connect(0), CLK => connect(1), CLR => n1, Q => 
         Q_net2_1);

   n1 <= '1';

   -- Forbidden Events
   FEC : if Timing_mesg generate
     F1 : IEEE.STD_LOGIC_COMPONENTS.MPWCK
	  generic map( tHigh => twCLK_H, tLow => twCLK_L)
	  port map( Clock => connect(1));

     F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
	  generic map( N => 1, tHold => thCLK_D)
	  port map( Data(1) => connect(0), Clock => connect(1));

     F3 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
	  generic map( N => 1, tSetup => tsuD_CLK)
	  port map( Data(1) => connect(0), Clock => connect(1));

   end generate FEC;

end FTSM;

configuration CFG_DFF_FTSM of DFF is
   for FTSM
   end for;
end CFG_DFF_FTSM;


----- CELL DFFC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity DFFC is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdCLB_Q_F                     :	Time := 590.630 ps;
      tpdCLK_Q_R                     :	Time := 2426.230 ps;
      tpdCLK_Q_F                     :	Time := 1898.930 ps;
      tpdCLB_QB_R                    :	Time := 100.000 ps;
      tpdCLB_QB_F                    :	Time := 2272.700 ps;
      tpdCLK_QB_R                    :	Time := 1424.740 ps;
      tpdCLK_QB_F                    :	Time := 1736.000 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 560.000 ps;
      twCLK_H                        :	Time := 980.000 ps;
      twCLK_L                        :	Time := 980.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end DFFC;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of DFFC is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tsuD_CLK: constant is "FEC/F3/tSetup";
   attribute PROPAGATE_VALUE of thCLK_D: constant is "FEC/F2/tHold";
   attribute PROPAGATE_VALUE of twCLK_L: constant is "FEC/F1/tLow";
   attribute PROPAGATE_VALUE of twCLK_H: constant is "FEC/F1/tHigh";
   attribute PROPAGATE_VALUE of tpdCLK_QB_F: constant is "U8/tHL, U8/tLH, " &
	"U9/tHL, U9/tLH";
   attribute PROPAGATE_VALUE of tpdCLK_QB_R: constant is "U8/tLH, U8/tHL, " &
	"U9/tLH, U9/tHL";
   attribute PROPAGATE_VALUE of tpdCLB_QB_F: constant is "U7/tLH";
   attribute PROPAGATE_VALUE of tpdCLB_QB_R: constant is "U7/tHL";
   attribute PROPAGATE_VALUE of tpdCLK_Q_F: constant is "U5/tLH, U5/tHL, " &
	"U6/tLH, U6/tHL";
   attribute PROPAGATE_VALUE of tpdCLK_Q_R: constant is "U4/tLH, U5/tHL, " &
	"U5/tLH, U6/tHL, U6/tLH";
   attribute PROPAGATE_VALUE of tpdCLB_Q_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdCLB_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdCLB_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdCLK_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdCLK_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_Q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_QB : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal net2 : STD_LOGIC;

   component INVMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

   component DFFLMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         D                              :  in    STD_LOGIC;
         CLK                            :  in    STD_LOGIC;
         CLR                            :  in    STD_LOGIC;
         Q                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(1));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdCLK_R, tHL => twdCLK_F)
	port map( Input => CLK, Output => connect(2));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdCLB_R, tHL => twdCLB_F)
	port map( Input => CLB, Output => connect(0));

   -- Intrinsic delay buffers
   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_Q_R, tHL => tpdCLB_Q_F)
	port map( Input => connect(0), Output => prop_Q(0));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_Q_R, tHL => tpdCLK_Q_R)
	port map( Input => connect(2), Output => prop_Q(1));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_Q_R, tHL => tpdCLK_Q_R)
	port map( Input => connect(1), Output => prop_Q(2));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLB_QB_F, tHL => tpdCLB_QB_R)
	port map( Input => connect(0), Output => prop_QB(0));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_QB_F, tHL => tpdCLK_QB_F)
	port map( Input => connect(2), Output => prop_QB(1));

   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_QB_F, tHL => tpdCLK_QB_F)
	port map( Input => connect(1), Output => prop_QB(2));

   -- Netlist
   U10 : INVMAC
	port map( I0 => net2, Y => QB);

   U11 : DFFLMAC
	port map( D => prop_QB(2), CLK => prop_QB(1), CLR => prop_QB(0), Q => 
         net2);

   U12 : DFFLMAC
	port map( D => prop_Q(2), CLK => prop_Q(1), CLR => prop_Q(0), Q => 
         Q);


   -- Forbidden Events
   FEC : if Timing_mesg generate
     F1 : IEEE.STD_LOGIC_COMPONENTS.MPWCK
	  generic map( tHigh => twCLK_H, tLow => twCLK_L)
	  port map( Clock => connect(2));

     F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
	  generic map( N => 1, tHold => thCLK_D)
	  port map( Data(1) => connect(1), Clock => connect(2));

     F3 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
	  generic map( N => 1, tSetup => tsuD_CLK)
	  port map( Data(1) => connect(1), Clock => connect(2));

   end generate FEC;

end FTSM;

configuration CFG_DFFC_FTSM of DFFC is
   for FTSM
   end for;
end CFG_DFFC_FTSM;


----- CELL DFFP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity DFFP is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdPRB_Q_R                     :	Time := 806.750 ps;
      tpdCLK_Q_R                     :	Time := 1984.310 ps;
      tpdCLK_Q_F                     :	Time := 1904.280 ps;
      tpdPRB_QB_F                    :	Time := 477.540 ps;
      tpdCLK_QB_R                    :	Time := 1542.680 ps;
      tpdCLK_QB_F                    :	Time := 1658.400 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 460.000 ps;
      twCLK_H                        :	Time := 880.000 ps;
      twCLK_L                        :	Time := 880.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end DFFP;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of DFFP is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tsuD_CLK: constant is "FEC/F3/tSetup";
   attribute PROPAGATE_VALUE of thCLK_D: constant is "FEC/F2/tHold";
   attribute PROPAGATE_VALUE of twCLK_L: constant is "FEC/F1/tLow";
   attribute PROPAGATE_VALUE of twCLK_H: constant is "FEC/F1/tHigh";
   attribute PROPAGATE_VALUE of tpdCLK_QB_F: constant is "U8/tHL, U8/tLH, " &
	"U9/tHL, U9/tLH";
   attribute PROPAGATE_VALUE of tpdCLK_QB_R: constant is "U7/tLH, U8/tLH, " &
	"U8/tHL, U9/tLH, U9/tHL";
   attribute PROPAGATE_VALUE of tpdPRB_QB_F: constant is "U7/tHL";
   attribute PROPAGATE_VALUE of tpdCLK_Q_R: constant is "U5/tHL, U5/tLH, " &
	"U6/tHL, U6/tLH";
   attribute PROPAGATE_VALUE of tpdCLK_Q_F: constant is "U4/tLH, U5/tLH, " &
	"U5/tHL, U6/tLH, U6/tHL";
   attribute PROPAGATE_VALUE of tpdPRB_Q_R: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdPRB_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdPRB_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdCLK_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdCLK_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_Q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_QB : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal n1 : STD_LOGIC;

   component DFFSRLQ_11MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         D                              :  in    STD_LOGIC;
         CLK                            :  in    STD_LOGIC;
         CLR                            :  in    STD_LOGIC;
         PRE                            :  in    STD_LOGIC;
         Q                              :  out   STD_LOGIC);
   end component;

   component DFFSRL_00MAC
      generic(
         tpdQ_R                         :  Time := 0 ns;
         tpdQ_F                         :  Time := 0 ns;
         tpdQN_R                        :  Time := 0 ns;
         tpdQN_F                        :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         D                              :  in    STD_LOGIC;
         CLK                            :  in    STD_LOGIC;
         CLR                            :  in    STD_LOGIC;
         PRE                            :  in    STD_LOGIC;
         Q                              :  out   STD_LOGIC;
         QN                             :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(1));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdCLK_R, tHL => twdCLK_F)
	port map( Input => CLK, Output => connect(2));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdPRB_R, tHL => twdPRB_F)
	port map( Input => PRB, Output => connect(0));

   -- Intrinsic delay buffers
   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_Q_F, tHL => tpdPRB_Q_R)
	port map( Input => connect(0), Output => prop_Q(0));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_Q_R, tHL => tpdCLK_Q_R)
	port map( Input => connect(2), Output => prop_Q(1));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_Q_R, tHL => tpdCLK_Q_R)
	port map( Input => connect(1), Output => prop_Q(2));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_QB_R, tHL => tpdPRB_QB_F)
	port map( Input => connect(0), Output => prop_QB(0));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_QB_F, tHL => tpdCLK_QB_F)
	port map( Input => connect(2), Output => prop_QB(1));

   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_QB_F, tHL => tpdCLK_QB_F)
	port map( Input => connect(1), Output => prop_QB(2));

   -- Netlist
   U10 : DFFSRLQ_11MAC
	port map( D => prop_Q(2), CLK => prop_Q(1), CLR => n1, PRE => prop_Q(
         0), Q => Q);

   n1 <= '1';
   U11 : DFFSRL_00MAC
	port map( D => prop_QB(2), CLK => prop_QB(1), CLR => n1, PRE => 
         prop_QB(0), Q => open, QN => QB);


   -- Forbidden Events
   FEC : if Timing_mesg generate
     F1 : IEEE.STD_LOGIC_COMPONENTS.MPWCK
	  generic map( tHigh => twCLK_H, tLow => twCLK_L)
	  port map( Clock => connect(2));

     F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
	  generic map( N => 1, tHold => thCLK_D)
	  port map( Data(1) => connect(1), Clock => connect(2));

     F3 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
	  generic map( N => 1, tSetup => tsuD_CLK)
	  port map( Data(1) => connect(1), Clock => connect(2));

   end generate FEC;

end FTSM;

configuration CFG_DFFP_FTSM of DFFP is
   for FTSM
   end for;
end CFG_DFFP_FTSM;


----- CELL DFFPC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity DFFPC is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdPRB_Q_R                     :	Time := 1152.300 ps;
      tpdCLB_Q_F                     :	Time := 514.590 ps;
      tpdCLK_Q_R                     :	Time := 2547.160 ps;
      tpdCLK_Q_F                     :	Time := 2043.240 ps;
      tpdPRB_QB_F                    :	Time := 419.190 ps;
      tpdCLB_QB_R                    :	Time := 1587.030 ps;
      tpdCLK_QB_R                    :	Time := 1556.220 ps;
      tpdCLK_QB_F                    :	Time := 1901.760 ps;
      thCLK_D                        :	Time := 0.000 ps;
      tsuD_CLK                       :	Time := 512.970 ps;
      twCLK_H                        :	Time := 1050.000 ps;
      twCLK_L                        :	Time := 1050.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdCLK_R                       :	Time := 0.000 ps;
      twdCLK_F                       :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      CLK                            :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end DFFPC;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of DFFPC is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tsuD_CLK: constant is "FEC/F3/tSetup";
   attribute PROPAGATE_VALUE of thCLK_D: constant is "FEC/F2/tHold";
   attribute PROPAGATE_VALUE of twCLK_L: constant is "FEC/F1/tLow";
   attribute PROPAGATE_VALUE of twCLK_H: constant is "FEC/F1/tHigh";
   attribute PROPAGATE_VALUE of tpdCLK_QB_F: constant is "U11/tHL, U11/tLH, " &
	"U12/tHL, U12/tLH";
   attribute PROPAGATE_VALUE of tpdCLK_QB_R: constant is "U11/tLH, U11/tHL, " &
	"U12/tLH, U12/tHL";
   attribute PROPAGATE_VALUE of tpdCLB_QB_R: constant is "U9/tLH, U10/tHL";
   attribute PROPAGATE_VALUE of tpdPRB_QB_F: constant is "U9/tHL, U10/tLH";
   attribute PROPAGATE_VALUE of tpdCLK_Q_R: constant is "U7/tHL, U7/tLH, " &
	"U8/tHL, U8/tLH";
   attribute PROPAGATE_VALUE of tpdCLK_Q_F: constant is "U7/tLH, U7/tHL, " &
	"U8/tLH, U8/tHL";
   attribute PROPAGATE_VALUE of tpdCLB_Q_F: constant is "U5/tLH, U6/tHL";
   attribute PROPAGATE_VALUE of tpdPRB_Q_R: constant is "U5/tHL, U6/tLH";
   attribute PROPAGATE_VALUE of twdCLB_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdCLB_R: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of twdPRB_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdPRB_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdCLK_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdCLK_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_Q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_QB : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');

   component DFFSRLQ_11MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         D                              :  in    STD_LOGIC;
         CLK                            :  in    STD_LOGIC;
         CLR                            :  in    STD_LOGIC;
         PRE                            :  in    STD_LOGIC;
         Q                              :  out   STD_LOGIC);
   end component;

   component DFFSRL_11MAC
      generic(
         tpdQ_R                         :  Time := 0 ns;
         tpdQ_F                         :  Time := 0 ns;
         tpdQN_R                        :  Time := 0 ns;
         tpdQN_F                        :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         D                              :  in    STD_LOGIC;
         CLK                            :  in    STD_LOGIC;
         CLR                            :  in    STD_LOGIC;
         PRE                            :  in    STD_LOGIC;
         Q                              :  out   STD_LOGIC;
         QN                             :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(2));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdCLK_R, tHL => twdCLK_F)
	port map( Input => CLK, Output => connect(3));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdPRB_R, tHL => twdPRB_F)
	port map( Input => PRB, Output => connect(0));

   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdCLB_R, tHL => twdCLB_F)
	port map( Input => CLB, Output => connect(1));

   -- Intrinsic delay buffers
   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLB_Q_F, tHL => tpdPRB_Q_R)
	port map( Input => connect(0), Output => prop_Q(0));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdPRB_Q_R, tHL => tpdCLB_Q_F)
	port map( Input => connect(1), Output => prop_Q(1));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_Q_R, tHL => tpdCLK_Q_R)
	port map( Input => connect(3), Output => prop_Q(2));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_Q_R, tHL => tpdCLK_Q_R)
	port map( Input => connect(2), Output => prop_Q(3));

   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLB_QB_R, tHL => tpdPRB_QB_F)
	port map( Input => connect(0), Output => prop_QB(0));

   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdPRB_QB_F, tHL => tpdCLB_QB_R)
	port map( Input => connect(1), Output => prop_QB(1));

   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_QB_F, tHL => tpdCLK_QB_F)
	port map( Input => connect(3), Output => prop_QB(2));

   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLK_QB_F, tHL => tpdCLK_QB_F)
	port map( Input => connect(2), Output => prop_QB(3));

   -- Netlist
   U13 : DFFSRLQ_11MAC
	port map( D => prop_Q(3), CLK => prop_Q(2), CLR => prop_Q(1), PRE => 
         prop_Q(0), Q => Q);

   U14 : DFFSRL_11MAC
	port map( D => prop_QB(3), CLK => prop_QB(2), CLR => prop_QB(1), PRE 
         => prop_QB(0), Q => open, QN => QB);


   -- Forbidden Events
   FEC : if Timing_mesg generate
     F1 : IEEE.STD_LOGIC_COMPONENTS.MPWCK
	  generic map( tHigh => twCLK_H, tLow => twCLK_L)
	  port map( Clock => connect(3));

     F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
	  generic map( N => 1, tHold => thCLK_D)
	  port map( Data(1) => connect(2), Clock => connect(3));

     F3 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
	  generic map( N => 1, tSetup => tsuD_CLK)
	  port map( Data(1) => connect(2), Clock => connect(3));

   end generate FEC;

end FTSM;

configuration CFG_DFFPC_FTSM of DFFPC is
   for FTSM
   end for;
end CFG_DFFPC_FTSM;


----- CELL INV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity INV is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 147.050 ps;
      tpdA_outb_F                    :	Time := 131.020 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end INV;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of INV is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U2/U1/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U2/U1/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');

   component INVMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   -- Netlist
   U2 : INVMAC
	generic map( tpdY_R => tpdA_outb_R, tpdY_F => tpdA_outb_F )
	port map( I0 => connect(0), Y => outb);


end FTSM;

configuration CFG_INV_FTSM of INV is
   for FTSM
   end for;
end CFG_INV_FTSM;


----- CELL INV2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity INV2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 143.010 ps;
      tpdA_out1_F                    :	Time := 133.030 ps;
      tpdB_out2_R                    :	Time := 142.700 ps;
      tpdB_out2_F                    :	Time := 132.800 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end INV2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of INV2 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is "U4/U1/tHL";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is "U4/U1/tLH";
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is "U3/U1/tHL";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is "U3/U1/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');

   component INVMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   -- Netlist
   U3 : INVMAC
	generic map( tpdY_R => tpdB_out2_R, tpdY_F => tpdB_out2_F )
	port map( I0 => connect(1), Y => out2);

   U4 : INVMAC
	generic map( tpdY_R => tpdA_out1_R, tpdY_F => tpdA_out1_F )
	port map( I0 => connect(0), Y => out1);


end FTSM;

configuration CFG_INV2_FTSM of INV2 is
   for FTSM
   end for;
end CFG_INV2_FTSM;


----- CELL INVZ -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity INVZ is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdOEB_outb_R                  :	Time := 0.000 ps;
      tpdOEB_outb_F                  :	Time := 172.430 ps;
      tpdOEB_outb_LZ                 :	Time := 0.000 ps;
      tpdOEB_outb_HZ                 :	Time := 172.430 ps;
      tpdA_outb_R                    :	Time := 204.660 ps;
      tpdA_outb_F                    :	Time := 191.380 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdOEB_R                       :	Time := 0.000 ps;
      twdOEB_F                       :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      OEB                            :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end INVZ;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of INVZ is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of tpdOEB_outb_F: constant is "U3/tHL, U3/tLH";
   attribute PROPAGATE_VALUE of tpdOEB_outb_HZ: constant is "U3/tLH, U3/tHL";
   attribute PROPAGATE_VALUE of tpdOEB_outb_LZ: constant is "U3/tLH, U3/tHL";
   attribute PROPAGATE_VALUE of tpdOEB_outb_R: constant is "U3/tLH, U3/tHL";
   attribute PROPAGATE_VALUE of twdOEB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdOEB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');

   component BUF3SHEMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         OE                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(1));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdOEB_R, tHL => twdOEB_F)
	port map( Input => OEB, Output => connect(0));

   -- Intrinsic delay buffers
   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdOEB_outb_F, tHL => tpdOEB_outb_F)
	port map( Input => connect(0), Output => prop_outb(0));

   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_R, tHL => tpdA_outb_F)
	port map( Input => connect(1), Output => prop_outb(1));

   -- Netlist
   U5 : BUF3SHEMAC
	port map( I0 => prop_outb(1), OE => prop_outb(0), Y => outb);


end FTSM;

configuration CFG_INVZ_FTSM of INVZ is
   for FTSM
   end for;
end CFG_INVZ_FTSM;


----- CELL LAT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity LAT is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdD_Q_R                       :	Time := 747.850 ps;
      tpdD_Q_F                       :	Time := 775.010 ps;
      tpdGB_Q_R                      :	Time := 1219.200 ps;
      tpdGB_Q_F                      :	Time := 1031.260 ps;
      tpdD_QB_R                      :	Time := 1019.590 ps;
      tpdD_QB_F                      :	Time := 950.320 ps;
      tpdGB_QB_R                     :	Time := 1434.270 ps;
      tpdGB_QB_F                     :	Time := 1227.970 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end LAT;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of LAT is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdGB_QB_R: constant is "U6/tHL, U6/tLH";
   attribute PROPAGATE_VALUE of tpdGB_QB_F: constant is "U6/tLH, U6/tHL";
   attribute PROPAGATE_VALUE of tpdD_QB_R: constant is "U5/tHL, U5/tLH";
   attribute PROPAGATE_VALUE of tpdD_QB_F: constant is "U5/tLH, U5/tHL";
   attribute PROPAGATE_VALUE of tpdGB_Q_R: constant is "U4/tHL, U4/tLH";
   attribute PROPAGATE_VALUE of tpdGB_Q_F: constant is "U4/tLH, U4/tHL";
   attribute PROPAGATE_VALUE of tpdD_Q_F: constant is "U3/tHL, U3/tLH";
   attribute PROPAGATE_VALUE of tpdD_Q_R: constant is "U3/tLH, U3/tHL";
   attribute PROPAGATE_VALUE of twdGB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdGB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_Q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_QB : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal n1, net2, n3, n4 : STD_LOGIC;

   component DLATLMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         D                              :  in    STD_LOGIC;
         G                              :  in    STD_LOGIC;
         CLR                            :  in    STD_LOGIC;
         Q                              :  out   STD_LOGIC);
   end component;

   component INVMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdGB_R, tHL => twdGB_F)
	port map( Input => GB, Output => connect(1));

   -- Intrinsic delay buffers
   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_Q_F, tHL => tpdD_Q_F)
	port map( Input => connect(0), Output => prop_Q(0));

   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdGB_Q_R, tHL => tpdGB_Q_R)
	port map( Input => connect(1), Output => prop_Q(1));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_QB_R, tHL => tpdD_QB_R)
	port map( Input => connect(0), Output => prop_QB(0));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdGB_QB_R, tHL => tpdGB_QB_R)
	port map( Input => connect(1), Output => prop_QB(1));

   -- Netlist
   U7 : DLATLMAC
	port map( D => prop_QB(0), G => n3, CLR => n1, Q => net2);

   n1 <= '1';
   U8 : DLATLMAC
	port map( D => prop_Q(0), G => n4, CLR => n1, Q => Q);

   U9 : INVMAC
	port map( I0 => prop_Q(1), Y => n4);

   U10 : INVMAC
	port map( I0 => prop_QB(1), Y => n3);

   U11 : INVMAC
	port map( I0 => net2, Y => QB);


end FTSM;

configuration CFG_LAT_FTSM of LAT is
   for FTSM
   end for;
end CFG_LAT_FTSM;


----- CELL LATC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity LATC is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdD_Q_R                       :	Time := 1284.890 ps;
      tpdD_Q_F                       :	Time := 1170.820 ps;
      tpdGB_Q_R                      :	Time := 1222.430 ps;
      tpdGB_Q_F                      :	Time := 1585.660 ps;
      tpdCLB_Q_F                     :	Time := 390.060 ps;
      tpdD_QB_R                      :	Time := 976.820 ps;
      tpdD_QB_F                      :	Time := 1002.540 ps;
      tpdGB_QB_R                     :	Time := 1032.910 ps;
      tpdGB_QB_F                     :	Time := 1297.520 ps;
      tpdCLB_QB_F                    :	Time := 201.080 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end LATC;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of LATC is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdCLB_QB_F: constant is "U9/tLH";
   attribute PROPAGATE_VALUE of tpdGB_QB_F: constant is "U8/tHL, U8/tLH";
   attribute PROPAGATE_VALUE of tpdGB_QB_R: constant is "U8/tLH, U8/tHL, " &
	"U9/tHL";
   attribute PROPAGATE_VALUE of tpdD_QB_F: constant is "U7/tHL, U7/tLH";
   attribute PROPAGATE_VALUE of tpdD_QB_R: constant is "U7/tLH, U7/tHL, " &
	"U9/tHL";
   attribute PROPAGATE_VALUE of tpdCLB_Q_F: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdGB_Q_F: constant is "U5/tHL, U5/tLH";
   attribute PROPAGATE_VALUE of tpdGB_Q_R: constant is "U5/tLH, U5/tHL, " &
	"U6/tLH";
   attribute PROPAGATE_VALUE of tpdD_Q_R: constant is "U4/tHL, U4/tLH, " &
	"U6/tLH";
   attribute PROPAGATE_VALUE of tpdD_Q_F: constant is "U4/tLH, U4/tHL";
   attribute PROPAGATE_VALUE of twdCLB_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdCLB_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdGB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdGB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_Q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_QB : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal net2, n1, n2 : STD_LOGIC;

   component DLATLMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         D                              :  in    STD_LOGIC;
         G                              :  in    STD_LOGIC;
         CLR                            :  in    STD_LOGIC;
         Q                              :  out   STD_LOGIC);
   end component;

   component INVMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdGB_R, tHL => twdGB_F)
	port map( Input => GB, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdCLB_R, tHL => twdCLB_F)
	port map( Input => CLB, Output => connect(2));

   -- Intrinsic delay buffers
   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_Q_R, tHL => tpdD_Q_R)
	port map( Input => connect(0), Output => prop_Q(0));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdGB_Q_F, tHL => tpdGB_Q_F)
	port map( Input => connect(1), Output => prop_Q(1));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_Q_R, tHL => tpdCLB_Q_F)
	port map( Input => connect(2), Output => prop_Q(2));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_QB_F, tHL => tpdD_QB_F)
	port map( Input => connect(0), Output => prop_QB(0));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdGB_QB_F, tHL => tpdGB_QB_F)
	port map( Input => connect(1), Output => prop_QB(1));

   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLB_QB_F, tHL => tpdGB_QB_R)
	port map( Input => connect(2), Output => prop_QB(2));

   -- Netlist
   U10 : DLATLMAC
	port map( D => prop_QB(0), G => n1, CLR => prop_QB(2), Q => net2);

   U11 : DLATLMAC
	port map( D => prop_Q(0), G => n2, CLR => prop_Q(2), Q => Q);

   U12 : INVMAC
	port map( I0 => prop_Q(1), Y => n2);

   U13 : INVMAC
	port map( I0 => prop_QB(1), Y => n1);

   U14 : INVMAC
	port map( I0 => net2, Y => QB);


end FTSM;

configuration CFG_LATC_FTSM of LATC is
   for FTSM
   end for;
end CFG_LATC_FTSM;


----- CELL LATP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity LATP is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdD_Q_R                       :	Time := 776.950 ps;
      tpdD_Q_F                       :	Time := 850.480 ps;
      tpdGB_Q_R                      :	Time := 1277.980 ps;
      tpdGB_Q_F                      :	Time := 1063.400 ps;
      tpdPRB_Q_R                     :	Time := 196.360 ps;
      tpdD_QB_R                      :	Time := 1145.520 ps;
      tpdD_QB_F                      :	Time := 980.720 ps;
      tpdGB_QB_R                     :	Time := 1517.700 ps;
      tpdGB_QB_F                     :	Time := 1247.490 ps;
      tpdPRB_QB_R                    :	Time := 100.000 ps;
      tpdPRB_QB_F                    :	Time := 388.620 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end LATP;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of LATP is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdPRB_QB_R: constant is "U9/tLH";
   attribute PROPAGATE_VALUE of tpdPRB_QB_F: constant is "U9/tHL";
   attribute PROPAGATE_VALUE of tpdGB_QB_R: constant is "U8/tHL, U8/tLH";
   attribute PROPAGATE_VALUE of tpdGB_QB_F: constant is "U8/tLH, U8/tHL";
   attribute PROPAGATE_VALUE of tpdD_QB_R: constant is "U7/tHL, U7/tLH";
   attribute PROPAGATE_VALUE of tpdD_QB_F: constant is "U7/tLH, U7/tHL";
   attribute PROPAGATE_VALUE of tpdPRB_Q_R: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdGB_Q_R: constant is "U5/tHL, U5/tLH";
   attribute PROPAGATE_VALUE of tpdGB_Q_F: constant is "U5/tLH, U5/tHL, " &
	"U6/tLH";
   attribute PROPAGATE_VALUE of tpdD_Q_F: constant is "U4/tHL, U4/tLH, " &
	"U6/tLH";
   attribute PROPAGATE_VALUE of tpdD_Q_R: constant is "U4/tLH, U4/tHL";
   attribute PROPAGATE_VALUE of twdPRB_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdPRB_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdGB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdGB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_Q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_QB : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal n1, n2, n3, net2 : STD_LOGIC;

   component DLATSRLQ_11MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         D                              :  in    STD_LOGIC;
         G                              :  in    STD_LOGIC;
         CLR                            :  in    STD_LOGIC;
         PRE                            :  in    STD_LOGIC;
         Q                              :  out   STD_LOGIC);
   end component;

   component INVMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdGB_R, tHL => twdGB_F)
	port map( Input => GB, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdPRB_R, tHL => twdPRB_F)
	port map( Input => PRB, Output => connect(2));

   -- Intrinsic delay buffers
   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_Q_F, tHL => tpdD_Q_F)
	port map( Input => connect(0), Output => prop_Q(0));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdGB_Q_R, tHL => tpdGB_Q_R)
	port map( Input => connect(1), Output => prop_Q(1));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdGB_Q_F, tHL => tpdPRB_Q_R)
	port map( Input => connect(2), Output => prop_Q(2));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_QB_R, tHL => tpdD_QB_R)
	port map( Input => connect(0), Output => prop_QB(0));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdGB_QB_R, tHL => tpdGB_QB_R)
	port map( Input => connect(1), Output => prop_QB(1));

   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdPRB_QB_R, tHL => tpdPRB_QB_F)
	port map( Input => connect(2), Output => prop_QB(2));

   -- Netlist
   U10 : DLATSRLQ_11MAC
	port map( D => prop_QB(0), G => n1, CLR => n2, PRE => prop_QB(2), Q => 
         net2);

   U11 : INVMAC
	port map( I0 => prop_QB(1), Y => n1);

   n2 <= '1';
   U12 : DLATSRLQ_11MAC
	port map( D => prop_Q(0), G => n3, CLR => n2, PRE => prop_Q(2), Q => 
         Q);

   U13 : INVMAC
	port map( I0 => prop_Q(1), Y => n3);

   U14 : INVMAC
	port map( I0 => net2, Y => QB);


end FTSM;

configuration CFG_LATP_FTSM of LATP is
   for FTSM
   end for;
end CFG_LATP_FTSM;


----- CELL LATPC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity LATPC is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdD_Q_R                       :	Time := 961.030 ps;
      tpdD_Q_F                       :	Time := 954.510 ps;
      tpdGB_Q_R                      :	Time := 1399.670 ps;
      tpdGB_Q_F                      :	Time := 1244.420 ps;
      tpdPRB_Q_R                     :	Time := 279.160 ps;
      tpdCLB_Q_F                     :	Time := 625.340 ps;
      tpdD_QB_R                      :	Time := 1264.200 ps;
      tpdD_QB_F                      :	Time := 1219.990 ps;
      tpdGB_QB_R                     :	Time := 1687.280 ps;
      tpdGB_QB_F                     :	Time := 1484.680 ps;
      tpdPRB_QB_R                    :	Time := 100.000 ps;
      tpdPRB_QB_F                    :	Time := 489.970 ps;
      tpdCLB_QB_R                    :	Time := 907.590 ps;
      tpdCLB_QB_F                    :	Time := 100.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps;
      twdGB_R                        :	Time := 0.000 ps;
      twdGB_F                        :	Time := 0.000 ps;
      twdPRB_R                       :	Time := 0.000 ps;
      twdPRB_F                       :	Time := 0.000 ps;
      twdCLB_R                       :	Time := 0.000 ps;
      twdCLB_F                       :	Time := 0.000 ps);

   port(
      D                              :	in    STD_LOGIC;
      GB                             :	in    STD_LOGIC;
      PRB                            :	in    STD_LOGIC;
      CLB                            :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QB                             :	out   STD_LOGIC);
end LATPC;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of LATPC is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdCLB_QB_F: constant is "U12/tLH";
   attribute PROPAGATE_VALUE of tpdCLB_QB_R: constant is "U12/tHL";
   attribute PROPAGATE_VALUE of tpdPRB_QB_R: constant is "U11/tLH";
   attribute PROPAGATE_VALUE of tpdPRB_QB_F: constant is "U11/tHL";
   attribute PROPAGATE_VALUE of tpdGB_QB_R: constant is "U10/tHL, U10/tLH";
   attribute PROPAGATE_VALUE of tpdGB_QB_F: constant is "U10/tLH, U10/tHL";
   attribute PROPAGATE_VALUE of tpdD_QB_R: constant is "U9/tHL, U9/tLH";
   attribute PROPAGATE_VALUE of tpdD_QB_F: constant is "U9/tLH, U9/tHL";
   attribute PROPAGATE_VALUE of tpdPRB_Q_R: constant is "U7/tHL, U8/tLH";
   attribute PROPAGATE_VALUE of tpdCLB_Q_F: constant is "U7/tLH, U8/tHL";
   attribute PROPAGATE_VALUE of tpdGB_Q_R: constant is "U6/tHL, U6/tLH, " &
	"U8/tLH";
   attribute PROPAGATE_VALUE of tpdGB_Q_F: constant is "U6/tLH, U6/tHL, " &
	"U7/tLH";
   attribute PROPAGATE_VALUE of tpdD_Q_R: constant is "U5/tHL, U5/tLH, " &
	"U8/tLH";
   attribute PROPAGATE_VALUE of tpdD_Q_F: constant is "U5/tLH, U5/tHL, " &
	"U7/tLH";
   attribute PROPAGATE_VALUE of twdCLB_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdCLB_R: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of twdPRB_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdPRB_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdGB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdGB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_Q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_QB : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal n1, n2 : STD_LOGIC;

   component DLATSRL_11MAC
      generic(
         tpdQ_R                         :  Time := 0 ns;
         tpdQ_F                         :  Time := 0 ns;
         tpdQN_R                        :  Time := 0 ns;
         tpdQN_F                        :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         D                              :  in    STD_LOGIC;
         G                              :  in    STD_LOGIC;
         CLR                            :  in    STD_LOGIC;
         PRE                            :  in    STD_LOGIC;
         Q                              :  out   STD_LOGIC;
         QN                             :  out   STD_LOGIC);
   end component;

   component DLATSRLQ_11MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         D                              :  in    STD_LOGIC;
         G                              :  in    STD_LOGIC;
         CLR                            :  in    STD_LOGIC;
         PRE                            :  in    STD_LOGIC;
         Q                              :  out   STD_LOGIC);
   end component;

   component INVMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdGB_R, tHL => twdGB_F)
	port map( Input => GB, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdPRB_R, tHL => twdPRB_F)
	port map( Input => PRB, Output => connect(2));

   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdCLB_R, tHL => twdCLB_F)
	port map( Input => CLB, Output => connect(3));

   -- Intrinsic delay buffers
   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_Q_R, tHL => tpdD_Q_R)
	port map( Input => connect(0), Output => prop_Q(0));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdGB_Q_R, tHL => tpdGB_Q_R)
	port map( Input => connect(1), Output => prop_Q(1));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdGB_Q_F, tHL => tpdPRB_Q_R)
	port map( Input => connect(2), Output => prop_Q(2));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdGB_Q_R, tHL => tpdCLB_Q_F)
	port map( Input => connect(3), Output => prop_Q(3));

   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_QB_R, tHL => tpdD_QB_R)
	port map( Input => connect(0), Output => prop_QB(0));

   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdGB_QB_R, tHL => tpdGB_QB_R)
	port map( Input => connect(1), Output => prop_QB(1));

   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdPRB_QB_R, tHL => tpdPRB_QB_F)
	port map( Input => connect(2), Output => prop_QB(2));

   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdCLB_QB_F, tHL => tpdCLB_QB_R)
	port map( Input => connect(3), Output => prop_QB(3));

   -- Netlist
   U13 : DLATSRL_11MAC
	port map( D => prop_QB(0), G => n2, CLR => prop_QB(3), PRE => prop_QB(
         2), Q => open, QN => QB);

   U14 : DLATSRLQ_11MAC
	port map( D => prop_Q(0), G => n1, CLR => prop_Q(3), PRE => prop_Q(2), 
         Q => Q);

   U15 : INVMAC
	port map( I0 => prop_Q(1), Y => n1);

   U16 : INVMAC
	port map( I0 => prop_QB(1), Y => n2);


end FTSM;

configuration CFG_LATPC_FTSM of LATPC is
   for FTSM
   end for;
end CFG_LATPC_FTSM;


----- CELL MUX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity MUX2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 690.380 ps;
      tpdA_outb_F                    :	Time := 714.350 ps;
      tpdB_outb_R                    :	Time := 724.830 ps;
      tpdB_outb_F                    :	Time := 735.190 ps;
      tpdSEL_outb_R                  :	Time := 662.750 ps;
      tpdSEL_outb_F                  :	Time := 742.990 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdSEL_R                       :	Time := 0.000 ps;
      twdSEL_F                       :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      SEL                            :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end MUX2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of MUX2 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdSEL_outb_F: constant is "U6/tHL, U6/tLH";
   attribute PROPAGATE_VALUE of tpdSEL_outb_R: constant is "U6/tLH, U6/tHL";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdSEL_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdSEL_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');

   component MUX2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         S0                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdSEL_R, tHL => twdSEL_F)
	port map( Input => SEL, Output => connect(2));

   -- Intrinsic delay buffers
   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_R, tHL => tpdA_outb_F)
	port map( Input => connect(0), Output => prop_outb(0));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_outb_R, tHL => tpdB_outb_F)
	port map( Input => connect(1), Output => prop_outb(1));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdSEL_outb_F, tHL => tpdSEL_outb_F)
	port map( Input => connect(2), Output => prop_outb(2));

   -- Netlist
   U7 : MUX2MAC
	port map( I0 => prop_outb(1), I1 => prop_outb(0), S0 => prop_outb(2), 
         Y => outb);


end FTSM;

configuration CFG_MUX2_FTSM of MUX2 is
   for FTSM
   end for;
end CFG_MUX2_FTSM;


----- CELL NAND2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 170.120 ps;
      tpdA_outb_F                    :	Time := 215.380 ps;
      tpdB_outb_R                    :	Time := 160.430 ps;
      tpdB_outb_F                    :	Time := 205.670 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NAND2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NAND2 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');

   component NAND2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   -- Intrinsic delay buffers
   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_F, tHL => tpdA_outb_R)
	port map( Input => connect(0), Output => prop_outb(0));

   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_outb_F, tHL => tpdB_outb_R)
	port map( Input => connect(1), Output => prop_outb(1));

   -- Netlist
   U5 : NAND2MAC
	port map( I0 => prop_outb(0), I1 => prop_outb(1), Y => outb);


end FTSM;

configuration CFG_NAND2_FTSM of NAND2 is
   for FTSM
   end for;
end CFG_NAND2_FTSM;


----- CELL NAND2C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND2C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 209.250 ps;
      tpdA_out1_F                    :	Time := 291.390 ps;
      tpdB_out1_R                    :	Time := 219.340 ps;
      tpdB_out1_F                    :	Time := 297.390 ps;
      tpdA_out2_R                    :	Time := 534.840 ps;
      tpdA_out2_F                    :	Time := 399.520 ps;
      tpdB_out2_R                    :	Time := 539.370 ps;
      tpdB_out2_F                    :	Time := 410.850 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NAND2C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NAND2C is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_out1 : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_out2 : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');

   component AND2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

   component NAND2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   -- Intrinsic delay buffers
   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out1_F, tHL => tpdA_out1_R)
	port map( Input => connect(0), Output => prop_out1(0));

   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out1_F, tHL => tpdB_out1_R)
	port map( Input => connect(1), Output => prop_out1(1));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out2_R, tHL => tpdA_out2_F)
	port map( Input => connect(0), Output => prop_out2(0));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out2_R, tHL => tpdB_out2_F)
	port map( Input => connect(1), Output => prop_out2(1));

   -- Netlist
   U7 : AND2MAC
	port map( I0 => prop_out2(0), I1 => prop_out2(1), Y => out2);

   U8 : NAND2MAC
	port map( I0 => prop_out1(0), I1 => prop_out1(1), Y => out1);


end FTSM;

configuration CFG_NAND2C_FTSM of NAND2C is
   for FTSM
   end for;
end CFG_NAND2C_FTSM;


----- CELL NAND3 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND3 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 238.450 ps;
      tpdA_outb_F                    :	Time := 418.700 ps;
      tpdB_outb_R                    :	Time := 238.230 ps;
      tpdB_outb_F                    :	Time := 411.670 ps;
      tpdC_outb_R                    :	Time := 210.960 ps;
      tpdC_outb_F                    :	Time := 391.990 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NAND3;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NAND3 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdC_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdC_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');

   component NAND3MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdC_R, tHL => twdC_F)
	port map( Input => C, Output => connect(2));

   -- Intrinsic delay buffers
   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_F, tHL => tpdA_outb_R)
	port map( Input => connect(0), Output => prop_outb(0));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_outb_F, tHL => tpdB_outb_R)
	port map( Input => connect(1), Output => prop_outb(1));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_outb_F, tHL => tpdC_outb_R)
	port map( Input => connect(2), Output => prop_outb(2));

   -- Netlist
   U7 : NAND3MAC
	port map( I0 => prop_outb(1), I1 => prop_outb(2), I2 => prop_outb(0), 
         Y => outb);


end FTSM;

configuration CFG_NAND3_FTSM of NAND3 is
   for FTSM
   end for;
end CFG_NAND3_FTSM;


----- CELL NAND3C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND3C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 282.720 ps;
      tpdA_out1_F                    :	Time := 517.310 ps;
      tpdB_out1_R                    :	Time := 268.440 ps;
      tpdB_out1_F                    :	Time := 516.930 ps;
      tpdC_out1_R                    :	Time := 262.570 ps;
      tpdC_out1_F                    :	Time := 497.940 ps;
      tpdA_out2_R                    :	Time := 852.730 ps;
      tpdA_out2_F                    :	Time := 466.010 ps;
      tpdB_out2_R                    :	Time := 808.550 ps;
      tpdB_out2_F                    :	Time := 452.120 ps;
      tpdC_out2_R                    :	Time := 838.570 ps;
      tpdC_out2_F                    :	Time := 482.040 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NAND3C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NAND3C is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdC_out2_R: constant is "U9/tLH";
   attribute PROPAGATE_VALUE of tpdC_out2_F: constant is "U9/tHL";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is "U8/tLH";
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is "U8/tHL";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is "U7/tLH";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is "U7/tHL";
   attribute PROPAGATE_VALUE of tpdC_out1_F: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdC_out1_R: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdC_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdC_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_out1 : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_out2 : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');

   component AND3MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

   component NAND3MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdC_R, tHL => twdC_F)
	port map( Input => C, Output => connect(2));

   -- Intrinsic delay buffers
   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out1_F, tHL => tpdA_out1_R)
	port map( Input => connect(0), Output => prop_out1(0));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out1_F, tHL => tpdB_out1_R)
	port map( Input => connect(1), Output => prop_out1(1));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_out1_F, tHL => tpdC_out1_R)
	port map( Input => connect(2), Output => prop_out1(2));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out2_R, tHL => tpdA_out2_F)
	port map( Input => connect(0), Output => prop_out2(0));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out2_R, tHL => tpdB_out2_F)
	port map( Input => connect(1), Output => prop_out2(1));

   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_out2_R, tHL => tpdC_out2_F)
	port map( Input => connect(2), Output => prop_out2(2));

   -- Netlist
   U10 : AND3MAC
	port map( I0 => prop_out2(1), I1 => prop_out2(2), I2 => prop_out2(0), 
         Y => out2);

   U11 : NAND3MAC
	port map( I0 => prop_out1(1), I1 => prop_out1(2), I2 => prop_out1(0), 
         Y => out1);


end FTSM;

configuration CFG_NAND3C_FTSM of NAND3C is
   for FTSM
   end for;
end CFG_NAND3C_FTSM;


----- CELL NAND4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND4 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 256.650 ps;
      tpdA_outb_F                    :	Time := 564.250 ps;
      tpdB_outb_R                    :	Time := 248.930 ps;
      tpdB_outb_F                    :	Time := 561.040 ps;
      tpdC_outb_R                    :	Time := 227.350 ps;
      tpdC_outb_F                    :	Time := 542.560 ps;
      tpdD_outb_R                    :	Time := 224.720 ps;
      tpdD_outb_F                    :	Time := 510.020 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NAND4;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NAND4 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_outb_F: constant is "U8/tLH";
   attribute PROPAGATE_VALUE of tpdD_outb_R: constant is "U8/tHL";
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is "U7/tLH";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is "U7/tHL";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of twdC_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdC_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');

   component NAND4MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         I3                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdC_R, tHL => twdC_F)
	port map( Input => C, Output => connect(2));

   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(3));

   -- Intrinsic delay buffers
   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_F, tHL => tpdA_outb_R)
	port map( Input => connect(0), Output => prop_outb(0));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_outb_F, tHL => tpdB_outb_R)
	port map( Input => connect(1), Output => prop_outb(1));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_outb_F, tHL => tpdC_outb_R)
	port map( Input => connect(2), Output => prop_outb(2));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_outb_F, tHL => tpdD_outb_R)
	port map( Input => connect(3), Output => prop_outb(3));

   -- Netlist
   U9 : NAND4MAC
	port map( I0 => prop_outb(0), I1 => prop_outb(1), I2 => prop_outb(2), 
         I3 => prop_outb(3), Y => outb);


end FTSM;

configuration CFG_NAND4_FTSM of NAND4 is
   for FTSM
   end for;
end CFG_NAND4_FTSM;


----- CELL NAND4C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NAND4C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 299.790 ps;
      tpdA_out1_F                    :	Time := 695.020 ps;
      tpdB_out1_R                    :	Time := 290.950 ps;
      tpdB_out1_F                    :	Time := 690.690 ps;
      tpdC_out1_R                    :	Time := 279.570 ps;
      tpdC_out1_F                    :	Time := 670.230 ps;
      tpdD_out1_R                    :	Time := 302.000 ps;
      tpdD_out1_F                    :	Time := 635.750 ps;
      tpdA_out2_R                    :	Time := 1060.930 ps;
      tpdA_out2_F                    :	Time := 486.440 ps;
      tpdB_out2_R                    :	Time := 1055.040 ps;
      tpdB_out2_F                    :	Time := 470.520 ps;
      tpdC_out2_R                    :	Time := 1004.560 ps;
      tpdC_out2_F                    :	Time := 454.790 ps;
      tpdD_out2_R                    :	Time := 976.920 ps;
      tpdD_out2_F                    :	Time := 495.330 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NAND4C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NAND4C is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_out2_R: constant is "U12/tLH";
   attribute PROPAGATE_VALUE of tpdD_out2_F: constant is "U12/tHL";
   attribute PROPAGATE_VALUE of tpdC_out2_R: constant is "U11/tLH";
   attribute PROPAGATE_VALUE of tpdC_out2_F: constant is "U11/tHL";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is "U10/tLH";
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is "U10/tHL";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is "U9/tLH";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is "U9/tHL";
   attribute PROPAGATE_VALUE of tpdD_out1_F: constant is "U8/tLH";
   attribute PROPAGATE_VALUE of tpdD_out1_R: constant is "U8/tHL";
   attribute PROPAGATE_VALUE of tpdC_out1_F: constant is "U7/tLH";
   attribute PROPAGATE_VALUE of tpdC_out1_R: constant is "U7/tHL";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of twdC_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdC_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_out1 : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_out2 : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');

   component AND4MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         I3                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

   component NAND4MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         I3                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdC_R, tHL => twdC_F)
	port map( Input => C, Output => connect(2));

   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(3));

   -- Intrinsic delay buffers
   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out1_F, tHL => tpdA_out1_R)
	port map( Input => connect(0), Output => prop_out1(0));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out1_F, tHL => tpdB_out1_R)
	port map( Input => connect(1), Output => prop_out1(1));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_out1_F, tHL => tpdC_out1_R)
	port map( Input => connect(2), Output => prop_out1(2));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_out1_F, tHL => tpdD_out1_R)
	port map( Input => connect(3), Output => prop_out1(3));

   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out2_R, tHL => tpdA_out2_F)
	port map( Input => connect(0), Output => prop_out2(0));

   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out2_R, tHL => tpdB_out2_F)
	port map( Input => connect(1), Output => prop_out2(1));

   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_out2_R, tHL => tpdC_out2_F)
	port map( Input => connect(2), Output => prop_out2(2));

   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_out2_R, tHL => tpdD_out2_F)
	port map( Input => connect(3), Output => prop_out2(3));

   -- Netlist
   U13 : AND4MAC
	port map( I0 => prop_out2(0), I1 => prop_out2(1), I2 => prop_out2(2), 
         I3 => prop_out2(3), Y => out2);

   U14 : NAND4MAC
	port map( I0 => prop_out1(0), I1 => prop_out1(1), I2 => prop_out1(2), 
         I3 => prop_out1(3), Y => out1);


end FTSM;

configuration CFG_NAND4C_FTSM of NAND4C is
   for FTSM
   end for;
end CFG_NAND4C_FTSM;


----- CELL NOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 306.120 ps;
      tpdA_outb_F                    :	Time := 180.470 ps;
      tpdB_outb_R                    :	Time := 246.340 ps;
      tpdB_outb_F                    :	Time := 144.220 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NOR2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NOR2 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');

   component NOR2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   -- Intrinsic delay buffers
   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_F, tHL => tpdA_outb_R)
	port map( Input => connect(0), Output => prop_outb(0));

   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_outb_F, tHL => tpdB_outb_R)
	port map( Input => connect(1), Output => prop_outb(1));

   -- Netlist
   U5 : NOR2MAC
	port map( I0 => prop_outb(0), I1 => prop_outb(1), Y => outb);


end FTSM;

configuration CFG_NOR2_FTSM of NOR2 is
   for FTSM
   end for;
end CFG_NOR2_FTSM;


----- CELL NOR2C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR2C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 348.620 ps;
      tpdA_out1_F                    :	Time := 170.630 ps;
      tpdB_out1_R                    :	Time := 419.440 ps;
      tpdB_out1_F                    :	Time := 218.670 ps;
      tpdA_out2_R                    :	Time := 416.760 ps;
      tpdA_out2_F                    :	Time := 550.810 ps;
      tpdB_out2_R                    :	Time := 412.490 ps;
      tpdB_out2_F                    :	Time := 641.700 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NOR2C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NOR2C is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_out1 : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_out2 : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');

   component OR2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

   component NOR2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   -- Intrinsic delay buffers
   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out1_F, tHL => tpdA_out1_R)
	port map( Input => connect(0), Output => prop_out1(0));

   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out1_F, tHL => tpdB_out1_R)
	port map( Input => connect(1), Output => prop_out1(1));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out2_R, tHL => tpdA_out2_F)
	port map( Input => connect(0), Output => prop_out2(0));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out2_R, tHL => tpdB_out2_F)
	port map( Input => connect(1), Output => prop_out2(1));

   -- Netlist
   U7 : OR2MAC
	port map( I0 => prop_out2(1), I1 => prop_out2(0), Y => out2);

   U8 : NOR2MAC
	port map( I0 => prop_out1(0), I1 => prop_out1(1), Y => out1);


end FTSM;

configuration CFG_NOR2C_FTSM of NOR2C is
   for FTSM
   end for;
end CFG_NOR2C_FTSM;


----- CELL NOR3 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR3 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 638.190 ps;
      tpdA_outb_F                    :	Time := 237.180 ps;
      tpdB_outb_R                    :	Time := 598.690 ps;
      tpdB_outb_F                    :	Time := 221.450 ps;
      tpdC_outb_R                    :	Time := 410.680 ps;
      tpdC_outb_F                    :	Time := 164.140 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NOR3;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NOR3 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdC_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdC_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');

   component NOR3MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdC_R, tHL => twdC_F)
	port map( Input => C, Output => connect(2));

   -- Intrinsic delay buffers
   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_F, tHL => tpdA_outb_R)
	port map( Input => connect(0), Output => prop_outb(0));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_outb_F, tHL => tpdB_outb_R)
	port map( Input => connect(1), Output => prop_outb(1));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_outb_F, tHL => tpdC_outb_R)
	port map( Input => connect(2), Output => prop_outb(2));

   -- Netlist
   U7 : NOR3MAC
	port map( I0 => prop_outb(2), I1 => prop_outb(0), I2 => prop_outb(1), 
         Y => outb);


end FTSM;

configuration CFG_NOR3_FTSM of NOR3 is
   for FTSM
   end for;
end CFG_NOR3_FTSM;


----- CELL NOR3C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR3C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 827.690 ps;
      tpdA_out1_F                    :	Time := 275.870 ps;
      tpdB_out1_R                    :	Time := 750.880 ps;
      tpdB_out1_F                    :	Time := 258.730 ps;
      tpdC_out1_R                    :	Time := 594.940 ps;
      tpdC_out1_F                    :	Time := 211.280 ps;
      tpdA_out2_R                    :	Time := 507.750 ps;
      tpdA_out2_F                    :	Time := 1086.060 ps;
      tpdB_out2_R                    :	Time := 500.950 ps;
      tpdB_out2_F                    :	Time := 1025.620 ps;
      tpdC_out2_R                    :	Time := 419.950 ps;
      tpdC_out2_F                    :	Time := 861.840 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NOR3C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NOR3C is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdC_out2_R: constant is "U9/tLH";
   attribute PROPAGATE_VALUE of tpdC_out2_F: constant is "U9/tHL";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is "U8/tLH";
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is "U8/tHL";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is "U7/tLH";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is "U7/tHL";
   attribute PROPAGATE_VALUE of tpdC_out1_F: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdC_out1_R: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdC_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdC_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_out1 : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
   signal prop_out2 : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');

   component OR3MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

   component NOR3MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdC_R, tHL => twdC_F)
	port map( Input => C, Output => connect(2));

   -- Intrinsic delay buffers
   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out1_F, tHL => tpdA_out1_R)
	port map( Input => connect(0), Output => prop_out1(0));

   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out1_F, tHL => tpdB_out1_R)
	port map( Input => connect(1), Output => prop_out1(1));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_out1_F, tHL => tpdC_out1_R)
	port map( Input => connect(2), Output => prop_out1(2));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out2_R, tHL => tpdA_out2_F)
	port map( Input => connect(0), Output => prop_out2(0));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out2_R, tHL => tpdB_out2_F)
	port map( Input => connect(1), Output => prop_out2(1));

   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_out2_R, tHL => tpdC_out2_F)
	port map( Input => connect(2), Output => prop_out2(2));

   -- Netlist
   U10 : OR3MAC
	port map( I0 => prop_out2(0), I1 => prop_out2(1), I2 => prop_out2(2), 
         Y => out2);

   U11 : NOR3MAC
	port map( I0 => prop_out1(2), I1 => prop_out1(0), I2 => prop_out1(1), 
         Y => out1);


end FTSM;

configuration CFG_NOR3C_FTSM of NOR3C is
   for FTSM
   end for;
end CFG_NOR3C_FTSM;


----- CELL NOR4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR4 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 936.830 ps;
      tpdA_outb_F                    :	Time := 227.580 ps;
      tpdB_outb_R                    :	Time := 880.970 ps;
      tpdB_outb_F                    :	Time := 239.880 ps;
      tpdC_outb_R                    :	Time := 730.940 ps;
      tpdC_outb_F                    :	Time := 212.470 ps;
      tpdD_outb_R                    :	Time := 465.420 ps;
      tpdD_outb_F                    :	Time := 169.030 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end NOR4;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NOR4 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_outb_F: constant is "U8/tLH";
   attribute PROPAGATE_VALUE of tpdD_outb_R: constant is "U8/tHL";
   attribute PROPAGATE_VALUE of tpdC_outb_F: constant is "U7/tLH";
   attribute PROPAGATE_VALUE of tpdC_outb_R: constant is "U7/tHL";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of twdC_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdC_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');

   component NOR4MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         I3                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdC_R, tHL => twdC_F)
	port map( Input => C, Output => connect(2));

   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(3));

   -- Intrinsic delay buffers
   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_F, tHL => tpdA_outb_R)
	port map( Input => connect(0), Output => prop_outb(0));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_outb_F, tHL => tpdB_outb_R)
	port map( Input => connect(1), Output => prop_outb(1));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_outb_F, tHL => tpdC_outb_R)
	port map( Input => connect(2), Output => prop_outb(2));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_outb_F, tHL => tpdD_outb_R)
	port map( Input => connect(3), Output => prop_outb(3));

   -- Netlist
   U9 : NOR4MAC
	port map( I0 => prop_outb(0), I1 => prop_outb(1), I2 => prop_outb(2), 
         I3 => prop_outb(3), Y => outb);


end FTSM;

configuration CFG_NOR4_FTSM of NOR4 is
   for FTSM
   end for;
end CFG_NOR4_FTSM;


----- CELL NOR4C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity NOR4C is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_out1_R                    :	Time := 1075.770 ps;
      tpdA_out1_F                    :	Time := 270.380 ps;
      tpdB_out1_R                    :	Time := 927.680 ps;
      tpdB_out1_F                    :	Time := 250.670 ps;
      tpdC_out1_R                    :	Time := 685.590 ps;
      tpdC_out1_F                    :	Time := 203.320 ps;
      tpdD_out1_R                    :	Time := 1134.410 ps;
      tpdD_out1_F                    :	Time := 269.150 ps;
      tpdA_out2_R                    :	Time := 492.230 ps;
      tpdA_out2_F                    :	Time := 1338.910 ps;
      tpdB_out2_R                    :	Time := 490.670 ps;
      tpdB_out2_F                    :	Time := 1200.570 ps;
      tpdC_out2_R                    :	Time := 421.030 ps;
      tpdC_out2_F                    :	Time := 948.620 ps;
      tpdD_out2_R                    :	Time := 513.930 ps;
      tpdD_out2_F                    :	Time := 1385.250 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      twdC_R                         :	Time := 0.000 ps;
      twdC_F                         :	Time := 0.000 ps;
      twdD_R                         :	Time := 0.000 ps;
      twdD_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC;
      out1                           :	out   STD_LOGIC;
      out2                           :	out   STD_LOGIC);
end NOR4C;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of NOR4C is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdD_out2_R: constant is "U12/tLH";
   attribute PROPAGATE_VALUE of tpdD_out2_F: constant is "U12/tHL";
   attribute PROPAGATE_VALUE of tpdC_out2_R: constant is "U11/tLH";
   attribute PROPAGATE_VALUE of tpdC_out2_F: constant is "U11/tHL";
   attribute PROPAGATE_VALUE of tpdB_out2_R: constant is "U10/tLH";
   attribute PROPAGATE_VALUE of tpdB_out2_F: constant is "U10/tHL";
   attribute PROPAGATE_VALUE of tpdA_out2_R: constant is "U9/tLH";
   attribute PROPAGATE_VALUE of tpdA_out2_F: constant is "U9/tHL";
   attribute PROPAGATE_VALUE of tpdD_out1_F: constant is "U8/tLH";
   attribute PROPAGATE_VALUE of tpdD_out1_R: constant is "U8/tHL";
   attribute PROPAGATE_VALUE of tpdC_out1_F: constant is "U7/tLH";
   attribute PROPAGATE_VALUE of tpdC_out1_R: constant is "U7/tHL";
   attribute PROPAGATE_VALUE of tpdB_out1_F: constant is "U6/tLH";
   attribute PROPAGATE_VALUE of tpdB_out1_R: constant is "U6/tHL";
   attribute PROPAGATE_VALUE of tpdA_out1_F: constant is "U5/tLH";
   attribute PROPAGATE_VALUE of tpdA_out1_R: constant is "U5/tHL";
   attribute PROPAGATE_VALUE of twdD_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of twdD_R: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of twdC_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdC_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_out1 : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
   signal prop_out2 : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');

   component OR4MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         I3                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

   component NOR4MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         I2                             :  in    STD_LOGIC;
         I3                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdC_R, tHL => twdC_F)
	port map( Input => C, Output => connect(2));

   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdD_R, tHL => twdD_F)
	port map( Input => D, Output => connect(3));

   -- Intrinsic delay buffers
   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out1_F, tHL => tpdA_out1_R)
	port map( Input => connect(0), Output => prop_out1(0));

   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out1_F, tHL => tpdB_out1_R)
	port map( Input => connect(1), Output => prop_out1(1));

   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_out1_F, tHL => tpdC_out1_R)
	port map( Input => connect(2), Output => prop_out1(2));

   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_out1_F, tHL => tpdD_out1_R)
	port map( Input => connect(3), Output => prop_out1(3));

   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_out2_R, tHL => tpdA_out2_F)
	port map( Input => connect(0), Output => prop_out2(0));

   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_out2_R, tHL => tpdB_out2_F)
	port map( Input => connect(1), Output => prop_out2(1));

   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdC_out2_R, tHL => tpdC_out2_F)
	port map( Input => connect(2), Output => prop_out2(2));

   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdD_out2_R, tHL => tpdD_out2_F)
	port map( Input => connect(3), Output => prop_out2(3));

   -- Netlist
   U13 : OR4MAC
	port map( I0 => prop_out2(2), I1 => prop_out2(3), I2 => prop_out2(0), 
         I3 => prop_out2(1), Y => out2);

   U14 : NOR4MAC
	port map( I0 => prop_out1(0), I1 => prop_out1(1), I2 => prop_out1(2), 
         I3 => prop_out1(3), Y => out1);


end FTSM;

configuration CFG_NOR4C_FTSM of NOR4C is
   for FTSM
   end for;
end CFG_NOR4C_FTSM;


----- CELL SINV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity SINV is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 395.840 ps;
      tpdA_outb_F                    :	Time := 350.680 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps);

   port(
      A                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end SINV;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of SINV is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U2/U1/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U2/U1/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');

   component INVMAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   -- Netlist
   U2 : INVMAC
	generic map( tpdY_R => tpdA_outb_R, tpdY_F => tpdA_outb_F )
	port map( I0 => connect(0), Y => outb);


end FTSM;

configuration CFG_SINV_FTSM of SINV is
   for FTSM
   end for;
end CFG_SINV_FTSM;


----- CELL XNOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.GS_TYPES.sdt_values_t;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity XNOR2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 581.840 ps;
      tpdA_outb_F                    :	Time := 523.040 ps;
      tpdB_outb_R                    :	Time := 345.970 ps;
      tpdB_outb_F                    :	Time := 266.650 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      SDT_outb_values : sdt_values_t :=
		(581.84 ps, 523.04 ps, 581.84 ps, 523.04 ps,
		 345.97 ps, 266.65 ps, 345.97 ps, 266.65 ps));

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end XNOR2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of XNOR2 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');

   component NXOR2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   -- Intrinsic delay buffers
   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_R, tHL => tpdA_outb_F)
	port map( Input => connect(0), Output => prop_outb(0));

   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_outb_R, tHL => tpdB_outb_F)
	port map( Input => connect(1), Output => prop_outb(1));

   -- Netlist
   U5 : NXOR2MAC
	port map( I0 => prop_outb(1), I1 => prop_outb(0), Y => outb);


end FTSM;

configuration CFG_XNOR2_FTSM of XNOR2 is
   for FTSM
   end for;
end CFG_XNOR2_FTSM;


----- CELL XOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.GS_TYPES.sdt_values_t;
library SYNOPSYS;
use SYNOPSYS.attributes.REAL_NAME;

-- entity declaration --
entity XOR2 is
   generic(
      Timing_mesg: Boolean := True;
      Timing_xgen: Boolean := False;
      tpdA_outb_R                    :	Time := 353.260 ps;
      tpdA_outb_F                    :	Time := 325.270 ps;
      tpdB_outb_R                    :	Time := 563.810 ps;
      tpdB_outb_F                    :	Time := 785.000 ps;
      twdA_R                         :	Time := 0.000 ps;
      twdA_F                         :	Time := 0.000 ps;
      twdB_R                         :	Time := 0.000 ps;
      twdB_F                         :	Time := 0.000 ps;
      SDT_outb_values : sdt_values_t :=
		(353.26 ps, 325.27 ps, 353.26 ps, 325.27 ps,
		 563.81 ps, 785.00 ps, 563.81 ps, 785.00 ps));

   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      outb                           :	out   STD_LOGIC);

   -- real names
   attribute REAL_NAME of outb : signal is "out";
end XOR2;

-- architecture body --
library IEEE_ASIC;
use IEEE.STD_LOGIC_MISC.all;
use SYNOPSYS.attributes.backplane;
use SYNOPSYS.attributes.PRIVATE;
use SYNOPSYS.attributes.ASIC_CELL;
use SYNOPSYS.attributes.PROPAGATE_VALUE;

architecture FTSM of XOR2 is
   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
   attribute PRIVATE of FTSM : architecture is TRUE;
   attribute ASIC_CELL of FTSM : architecture is TRUE;

   -- Backannotation attributes
   attribute PROPAGATE_VALUE of tpdB_outb_F: constant is "U4/tLH";
   attribute PROPAGATE_VALUE of tpdB_outb_R: constant is "U4/tHL";
   attribute PROPAGATE_VALUE of tpdA_outb_F: constant is "U3/tLH";
   attribute PROPAGATE_VALUE of tpdA_outb_R: constant is "U3/tHL";
   attribute PROPAGATE_VALUE of twdB_F: constant is "U2/tHL";
   attribute PROPAGATE_VALUE of twdB_R: constant is "U2/tLH";
   attribute PROPAGATE_VALUE of twdA_F: constant is "U1/tHL";
   attribute PROPAGATE_VALUE of twdA_R: constant is "U1/tLH";

   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
   signal prop_outb : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');

   component XOR2MAC
      generic(
         tpdY_R                         :  Time := 0 ns;
         tpdY_F                         :  Time := 0 ns;
         strn                           :  STRENGTH := strn_X01);
      port(
         I0                             :  in    STD_LOGIC;
         I1                             :  in    STD_LOGIC;
         Y                              :  out   STD_LOGIC);
   end component;

begin

   -- Extrinsic delay buffers
   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdA_R, tHL => twdA_F)
	port map( Input => A, Output => connect(0));

   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
	generic map( tLH => twdB_R, tHL => twdB_F)
	port map( Input => B, Output => connect(1));

   -- Intrinsic delay buffers
   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdA_outb_F, tHL => tpdA_outb_R)
	port map( Input => connect(0), Output => prop_outb(0));

   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
	generic map( tLH => tpdB_outb_F, tHL => tpdB_outb_R)
	port map( Input => connect(1), Output => prop_outb(1));

   -- Netlist
   U5 : XOR2MAC
	port map( I0 => prop_outb(1), I1 => prop_outb(0), Y => outb);


end FTSM;

configuration CFG_XOR2_FTSM of XOR2 is
   for FTSM
   end for;
end CFG_XOR2_FTSM;


---- end of library ----
