
----------------------------------------------------------------
-- 
-- Created by the Synopsys Library Compiler 1999.10
-- FILENAME     :    mAMIs050DL_VITAL.vhd
-- FILE CONTENTS:    Entity, Structural Architecture(VITAL),
--                   and Configuration
-- DATE CREATED :    Thu Jun 15 18:02:53 2000
-- 
-- LIBRARY      :    mAMIs050DL
-- REVISION     :    Not Specified
-- TECHNOLOGY   :    cmos
-- TIME SCALE   :    1 ps
-- LOGIC SYSTEM :    IEEE-1164
-- NOTES        :    VITAL, TimingChecksOn(TRUE), XGenerationOn(FALSE), TimingMessage(TRUE), OnDetect 
-- HISTORY      :
-- 
----------------------------------------------------------------

----- CELL AO22 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity AO22 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (879.730 ps, 716.920 ps);
      tpd_B_outb                     :	VitalDelayType01 := (940.160 ps, 729.560 ps);
      tpd_C_outb                     :	VitalDelayType01 := (640.380 ps, 534.000 ps);
      tpd_D_outb                     :	VitalDelayType01 := (622.660 ps, 551.380 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_C                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AO22 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end AO22;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of AO22 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (D_ipd, D, tipd_D);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := ((D_ipd) AND (C_ipd)) OR ((B_ipd) AND (A_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE),
                 1 => (B_ipd'last_event, tpd_B_outb, TRUE),
                 2 => (C_ipd'last_event, tpd_C_outb, TRUE),
                 3 => (D_ipd'last_event, tpd_D_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_AO22_VITAL of AO22 is
   for VITAL
   end for;
end CFG_AO22_VITAL;


----- CELL AOI22 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity AOI22 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (424.960 ps, 485.330 ps);
      tpd_B_outb                     :	VitalDelayType01 := (413.220 ps, 479.170 ps);
      tpd_C_outb                     :	VitalDelayType01 := (218.800 ps, 236.940 ps);
      tpd_D_outb                     :	VitalDelayType01 := (233.150 ps, 246.650 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_C                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AOI22 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end AOI22;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of AOI22 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (D_ipd, D, tipd_D);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (NOT (((D_ipd) AND (C_ipd)) OR ((B_ipd) AND (A_ipd))));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE),
                 1 => (B_ipd'last_event, tpd_B_outb, TRUE),
                 2 => (C_ipd'last_event, tpd_C_outb, TRUE),
                 3 => (D_ipd'last_event, tpd_D_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_AOI22_VITAL of AOI22 is
   for VITAL
   end for;
end CFG_AOI22_VITAL;


----- CELL BUF1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUF1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (336.960 ps, 352.160 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUF1 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end BUF1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of BUF1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := TO_X01(A_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_BUF1_VITAL of BUF1 is
   for VITAL
   end for;
end CFG_BUF1_VITAL;


----- CELL BUF4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUF4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (427.380 ps, 517.550 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUF4 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end BUF4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of BUF4 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := TO_X01(A_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_BUF4_VITAL of BUF4 is
   for VITAL
   end for;
end CFG_BUF4_VITAL;


----- CELL BUFI4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUFI4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (88.510 ps, 88.290 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUFI4 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end BUFI4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of BUFI4 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (NOT A_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_BUFI4_VITAL of BUFI4 is
   for VITAL
   end for;
end CFG_BUFI4_VITAL;


----- CELL BUFZ -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUFZ is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (833.610 ps, 752.680 ps);
      tpd_OEB_outb                   :	VitalDelayType01z := 
               (291.490 ps, 193.780 ps, 291.490 ps, 291.490 ps, 193.780 ps, 193.780 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_OEB                       :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      OEB                            :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUFZ : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end BUFZ;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of BUFZ is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OEB_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (OEB_ipd, OEB, tipd_OEB);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, OEB_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := VitalBUFIF0 (data => A_ipd,
              enable => OEB_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, VitalExtendToFillDelay(tpd_A_outb), TRUE),
                 1 => (OEB_ipd'last_event, VitalExtendToFillDelay(tpd_OEB_outb), TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;

end VITAL;

configuration CFG_BUFZ_VITAL of BUFZ is
   for VITAL
   end for;
end CFG_BUFZ_VITAL;


----- CELL DFF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity DFF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (1763.660 ps, 1535.840 ps);
      tpd_CLK_QB                     :	VitalDelayType01 := (1293.840 ps, 1513.420 ps);
      thold_D_CLK                    :	VitalDelayType := 0.000 ps;
      tsetup_D_CLK                   :	VitalDelayType := 450.000 ps;
      tpw_CLK_posedge                :	VitalDelayType := 750.000 ps;
      tpw_CLK_negedge                :	VitalDelayType := 750.000 ps;
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC;
      QB                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFF : entity is TRUE;
end DFF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of DFF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CLK_ipd)

   -- timing check results
   VARIABLE Tviol_D_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE CLK_delayed : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   ALIAS QB_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;
   VARIABLE QB_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_posedge,
          TimingData              => Tmkr_D_CLK_posedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ps,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ps,
          SetupHigh               => tsetup_D_CLK,
          SetupLow                => tsetup_D_CLK,
          HoldHigh                => thold_D_CLK,
          HoldLow                 => thold_D_CLK,
          CheckEnabled            => 
                           TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ps,
          Period                  => 0 ps,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_negedge,
          CheckEnabled            => 
                           TRUE,
          HeaderMsg               => InstancePath &"/DFF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_posedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => DFF_Q_tab,
        DataIn => (
               CLK_delayed, D_delayed, CLK_ipd));
      Q_zd := Violation XOR Q_zd;
      QB_zd := (NOT Q_zd);
      D_delayed := D_ipd;
      CLK_delayed := CLK_ipd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => QB,
       GlitchData => QB_GlitchData,
       OutSignalName => "QB",
       OutTemp => QB_zd,
       Paths => (0 => (CLK_ipd'last_event, tpd_CLK_QB, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_DFF_VITAL of DFF is
   for VITAL
   end for;
end CFG_DFF_VITAL;


----- CELL DFFC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity DFFC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_CLB_Q                      :	VitalDelayType01 := (2426.230 ps, 590.630 ps);
      tpd_CLK_Q                      :	VitalDelayType01 := (2426.230 ps, 1898.930 ps);
      tpd_CLB_QB                     :	VitalDelayType01 := (100.000 ps, 2272.700 ps);
      tpd_CLK_QB                     :	VitalDelayType01 := (1424.740 ps, 1736.000 ps);
      thold_D_CLK                    :	VitalDelayType := 0.000 ps;
      tsetup_D_CLK                   :	VitalDelayType := 560.000 ps;
      tpw_CLK_posedge                :	VitalDelayType := 980.000 ps;
      tpw_CLK_negedge                :	VitalDelayType := 980.000 ps;
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_CLB                       :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      CLB                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC;
      QB                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFC : entity is TRUE;
end DFFC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of DFFC is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLB_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (CLB_ipd, CLB, tipd_CLB);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CLK_ipd, CLB_ipd)

   -- timing check results
   VARIABLE Tviol_D_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE CLK_delayed : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   ALIAS QB_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;
   VARIABLE QB_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_posedge,
          TimingData              => Tmkr_D_CLK_posedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ps,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ps,
          SetupHigh               => tsetup_D_CLK,
          SetupLow                => tsetup_D_CLK,
          HoldHigh                => thold_D_CLK,
          HoldLow                 => thold_D_CLK,
          CheckEnabled            => 
                           TO_X01((NOT CLB_ipd) ) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFC",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ps,
          Period                  => 0 ps,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_negedge,
          CheckEnabled            => 
                           TO_X01((NOT CLB_ipd) ) /= '1',
          HeaderMsg               => InstancePath &"/DFFC",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_posedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => DFFC_Q_tab,
        DataIn => (
               CLB_ipd, CLK_delayed, D_delayed, CLK_ipd));
      Q_zd := Violation XOR Q_zd;
      QB_zd := (NOT Q_zd);
      D_delayed := D_ipd;
      CLK_delayed := CLK_ipd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLB_ipd'last_event, tpd_CLB_Q, TRUE),
                 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => QB,
       GlitchData => QB_GlitchData,
       OutSignalName => "QB",
       OutTemp => QB_zd,
       Paths => (0 => (CLB_ipd'last_event, tpd_CLB_QB, TRUE),
                 1 => (CLK_ipd'last_event, tpd_CLK_QB, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_DFFC_VITAL of DFFC is
   for VITAL
   end for;
end CFG_DFFC_VITAL;


----- CELL DFFP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity DFFP is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_PRB_Q                      :	VitalDelayType01 := (806.750 ps, 1904.280 ps);
      tpd_CLK_Q                      :	VitalDelayType01 := (1984.310 ps, 1904.280 ps);
      tpd_PRB_QB                     :	VitalDelayType01 := (1542.680 ps, 477.540 ps);
      tpd_CLK_QB                     :	VitalDelayType01 := (1542.680 ps, 1658.400 ps);
      thold_D_CLK                    :	VitalDelayType := 0.000 ps;
      tsetup_D_CLK                   :	VitalDelayType := 460.000 ps;
      tpw_CLK_posedge                :	VitalDelayType := 880.000 ps;
      tpw_CLK_negedge                :	VitalDelayType := 880.000 ps;
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_PRB                       :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      PRB                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC;
      QB                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFP : entity is TRUE;
end DFFP;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of DFFP is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL PRB_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (PRB_ipd, PRB, tipd_PRB);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CLK_ipd, PRB_ipd)

   -- timing check results
   VARIABLE Tviol_D_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE CLK_delayed : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   ALIAS QB_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;
   VARIABLE QB_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_posedge,
          TimingData              => Tmkr_D_CLK_posedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ps,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ps,
          SetupHigh               => tsetup_D_CLK,
          SetupLow                => tsetup_D_CLK,
          HoldHigh                => thold_D_CLK,
          HoldLow                 => thold_D_CLK,
          CheckEnabled            => 
                           TO_X01((NOT PRB_ipd) ) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ps,
          Period                  => 0 ps,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_negedge,
          CheckEnabled            => 
                           TO_X01((NOT PRB_ipd) ) /= '1',
          HeaderMsg               => InstancePath &"/DFFP",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_posedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => DFFP_Q_tab,
        DataIn => (
               CLK_delayed, D_delayed, PRB_ipd, CLK_ipd));
      Q_zd := Violation XOR Q_zd;
      QB_zd := (NOT Q_zd);
      D_delayed := D_ipd;
      CLK_delayed := CLK_ipd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (PRB_ipd'last_event, tpd_PRB_Q, TRUE),
                 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => QB,
       GlitchData => QB_GlitchData,
       OutSignalName => "QB",
       OutTemp => QB_zd,
       Paths => (0 => (PRB_ipd'last_event, tpd_PRB_QB, TRUE),
                 1 => (CLK_ipd'last_event, tpd_CLK_QB, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_DFFP_VITAL of DFFP is
   for VITAL
   end for;
end CFG_DFFP_VITAL;


----- CELL DFFPC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity DFFPC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_PRB_Q                      :	VitalDelayType01 := (1152.300 ps, 514.590 ps);
      tpd_CLB_Q                      :	VitalDelayType01 := (1152.300 ps, 514.590 ps);
      tpd_CLK_Q                      :	VitalDelayType01 := (2547.160 ps, 2043.240 ps);
      tpd_PRB_QB                     :	VitalDelayType01 := (1587.030 ps, 419.190 ps);
      tpd_CLB_QB                     :	VitalDelayType01 := (1587.030 ps, 419.190 ps);
      tpd_CLK_QB                     :	VitalDelayType01 := (1556.220 ps, 1901.760 ps);
      thold_D_CLK                    :	VitalDelayType := 0.000 ps;
      tsetup_D_CLK                   :	VitalDelayType := 512.970 ps;
      tpw_CLK_posedge                :	VitalDelayType := 1050.000 ps;
      tpw_CLK_negedge                :	VitalDelayType := 1050.000 ps;
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_PRB                       :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_CLB                       :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      PRB                            :	in    STD_ULOGIC;
      CLB                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC;
      QB                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFPC : entity is TRUE;
end DFFPC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of DFFPC is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL PRB_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLB_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (PRB_ipd, PRB, tipd_PRB);
   VitalWireDelay (CLB_ipd, CLB, tipd_CLB);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CLK_ipd, PRB_ipd, CLB_ipd)

   -- timing check results
   VARIABLE Tviol_D_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE PrevData_QB : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE D_delayed : STD_ULOGIC := 'X';
   VARIABLE CLK_delayed : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   ALIAS QB_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;
   VARIABLE QB_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_posedge,
          TimingData              => Tmkr_D_CLK_posedge,
          TestSignal              => D_ipd,
          TestSignalName          => "D",
          TestDelay               => 0 ps,
          RefSignal               => CLK_ipd,
          RefSignalName          => "CLK",
          RefDelay                => 0 ps,
          SetupHigh               => tsetup_D_CLK,
          SetupLow                => tsetup_D_CLK,
          HoldHigh                => thold_D_CLK,
          HoldLow                 => thold_D_CLK,
          CheckEnabled            => 
                           TO_X01(( (NOT PRB_ipd) ) OR ( (NOT CLB_ipd) ) ) /=
                            '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFPC",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ps,
          Period                  => 0 ps,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_negedge,
          CheckEnabled            => 
                           TO_X01(( (NOT PRB_ipd) ) OR ( (NOT CLB_ipd) ) ) /=
                            '1',
          HeaderMsg               => InstancePath &"/DFFPC",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_posedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => DFFPC_Q_tab,
        DataIn => (
               CLB_ipd, CLK_delayed, D_delayed, CLK_ipd, PRB_ipd));
      Q_zd := Violation XOR Q_zd;
      VitalStateTable(
        Result => QB_zd,
        PreviousDataIn => PrevData_QB,
        StateTable => DFFPC_QB_tab,
        DataIn => (
               PRB_ipd, CLK_delayed, D_delayed, CLK_ipd, CLB_ipd));
      QB_zd := Violation XOR QB_zd;
      D_delayed := D_ipd;
      CLK_delayed := CLK_ipd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (PRB_ipd'last_event, tpd_PRB_Q, TRUE),
                 1 => (CLB_ipd'last_event, tpd_CLB_Q, TRUE),
                 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => QB,
       GlitchData => QB_GlitchData,
       OutSignalName => "QB",
       OutTemp => QB_zd,
       Paths => (0 => (PRB_ipd'last_event, tpd_PRB_QB, TRUE),
                 1 => (CLB_ipd'last_event, tpd_CLB_QB, TRUE),
                 2 => (CLK_ipd'last_event, tpd_CLK_QB, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_DFFPC_VITAL of DFFPC is
   for VITAL
   end for;
end CFG_DFFPC_VITAL;


----- CELL INV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity INV is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (147.050 ps, 131.020 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of INV : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end INV;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of INV is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (NOT A_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_INV_VITAL of INV is
   for VITAL
   end for;
end CFG_INV_VITAL;


----- CELL INV2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity INV2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_out1                     :	VitalDelayType01 := (143.010 ps, 133.030 ps);
      tpd_B_out2                     :	VitalDelayType01 := (142.700 ps, 132.800 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      out1                           :	out   STD_ULOGIC;
      out2                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of INV2 : entity is TRUE;
end INV2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of INV2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS out1_zd : STD_LOGIC is Results(1);
   ALIAS out2_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE out1_GlitchData	: VitalGlitchDataType;
   VARIABLE out2_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      out1_zd := (NOT A_ipd);
      out2_zd := (NOT B_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => out1,
       GlitchData => out1_GlitchData,
       OutSignalName => "out1",
       OutTemp => out1_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out1, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => out2,
       GlitchData => out2_GlitchData,
       OutSignalName => "out2",
       OutTemp => out2_zd,
       Paths => (0 => (B_ipd'last_event, tpd_B_out2, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_INV2_VITAL of INV2 is
   for VITAL
   end for;
end CFG_INV2_VITAL;


----- CELL INVZ -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity INVZ is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_OEB_outb                   :	VitalDelayType01z := 
               (0.000 ps, 172.430 ps, 0.000 ps, 0.000 ps, 172.430 ps, 172.430 ps);
      tpd_A_outb                     :	VitalDelayType01 := (204.660 ps, 191.380 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_OEB                       :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      OEB                            :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of INVZ : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end INVZ;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of INVZ is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OEB_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (OEB_ipd, OEB, tipd_OEB);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, OEB_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := VitalBUFIF0 (data => A_ipd,
              enable => (NOT OEB_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (OEB_ipd'last_event, VitalExtendToFillDelay(tpd_OEB_outb), TRUE),
                 1 => (A_ipd'last_event, VitalExtendToFillDelay(tpd_A_outb), TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;

end VITAL;

configuration CFG_INVZ_VITAL of INVZ is
   for VITAL
   end for;
end CFG_INVZ_VITAL;


----- CELL LAT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LAT is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (747.850 ps, 775.010 ps);
      tpd_GB_Q                       :	VitalDelayType01 := (1219.200 ps, 1031.260 ps);
      tpd_D_QB                       :	VitalDelayType01 := (1019.590 ps, 950.320 ps);
      tpd_GB_QB                      :	VitalDelayType01 := (1434.270 ps, 1227.970 ps);
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_GB                        :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      D                              :	in    STD_ULOGIC;
      GB                             :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC;
      QB                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LAT : entity is TRUE;
end LAT;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of LAT is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL GB_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (GB_ipd, GB, tipd_GB);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, GB_ipd)


   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 1);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   ALIAS QB_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;
   VARIABLE QB_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------

      -- no timing checks

      -------------------------
      --  Functionality Section
      -------------------------
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => LAT_Q_tab,
        DataIn => (
               GB_ipd, D_ipd));
      QB_zd := (NOT Q_zd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE),
                 1 => (GB_ipd'last_event, tpd_GB_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => QB,
       GlitchData => QB_GlitchData,
       OutSignalName => "QB",
       OutTemp => QB_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_QB, TRUE),
                 1 => (GB_ipd'last_event, tpd_GB_QB, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LAT_VITAL of LAT is
   for VITAL
   end for;
end CFG_LAT_VITAL;


----- CELL LATC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LATC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (1284.890 ps, 1170.820 ps);
      tpd_GB_Q                       :	VitalDelayType01 := (1222.430 ps, 1585.660 ps);
      tpd_CLB_Q                      :	VitalDelayType01 := (1284.890 ps, 390.060 ps);
      tpd_D_QB                       :	VitalDelayType01 := (976.820 ps, 1002.540 ps);
      tpd_GB_QB                      :	VitalDelayType01 := (1032.910 ps, 1297.520 ps);
      tpd_CLB_QB                     :	VitalDelayType01 := (1032.910 ps, 201.080 ps);
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_GB                        :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_CLB                       :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      D                              :	in    STD_ULOGIC;
      GB                             :	in    STD_ULOGIC;
      CLB                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC;
      QB                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LATC : entity is TRUE;
end LATC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of LATC is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL GB_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLB_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (GB_ipd, GB, tipd_GB);
   VitalWireDelay (CLB_ipd, CLB, tipd_CLB);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, GB_ipd, CLB_ipd)


   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   ALIAS QB_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;
   VARIABLE QB_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------

      -- no timing checks

      -------------------------
      --  Functionality Section
      -------------------------
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => LATC_Q_tab,
        DataIn => (
               CLB_ipd, GB_ipd, D_ipd));
      QB_zd := (NOT Q_zd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE),
                 1 => (GB_ipd'last_event, tpd_GB_Q, TRUE),
                 2 => (CLB_ipd'last_event, tpd_CLB_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => QB,
       GlitchData => QB_GlitchData,
       OutSignalName => "QB",
       OutTemp => QB_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_QB, TRUE),
                 1 => (GB_ipd'last_event, tpd_GB_QB, TRUE),
                 2 => (CLB_ipd'last_event, tpd_CLB_QB, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LATC_VITAL of LATC is
   for VITAL
   end for;
end CFG_LATC_VITAL;


----- CELL LATP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LATP is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (776.950 ps, 850.480 ps);
      tpd_GB_Q                       :	VitalDelayType01 := (1277.980 ps, 1063.400 ps);
      tpd_PRB_Q                      :	VitalDelayType01 := (196.360 ps, 1063.400 ps);
      tpd_D_QB                       :	VitalDelayType01 := (1145.520 ps, 980.720 ps);
      tpd_GB_QB                      :	VitalDelayType01 := (1517.700 ps, 1247.490 ps);
      tpd_PRB_QB                     :	VitalDelayType01 := (100.000 ps, 388.620 ps);
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_GB                        :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_PRB                       :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      D                              :	in    STD_ULOGIC;
      GB                             :	in    STD_ULOGIC;
      PRB                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC;
      QB                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LATP : entity is TRUE;
end LATP;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of LATP is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL GB_ipd	 : STD_ULOGIC := 'X';
   SIGNAL PRB_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (GB_ipd, GB, tipd_GB);
   VitalWireDelay (PRB_ipd, PRB, tipd_PRB);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, GB_ipd, PRB_ipd)


   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   ALIAS QB_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;
   VARIABLE QB_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------

      -- no timing checks

      -------------------------
      --  Functionality Section
      -------------------------
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => LATP_Q_tab,
        DataIn => (
               GB_ipd, D_ipd, PRB_ipd));
      QB_zd := (NOT Q_zd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE),
                 1 => (GB_ipd'last_event, tpd_GB_Q, TRUE),
                 2 => (PRB_ipd'last_event, tpd_PRB_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => QB,
       GlitchData => QB_GlitchData,
       OutSignalName => "QB",
       OutTemp => QB_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_QB, TRUE),
                 1 => (GB_ipd'last_event, tpd_GB_QB, TRUE),
                 2 => (PRB_ipd'last_event, tpd_PRB_QB, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LATP_VITAL of LATP is
   for VITAL
   end for;
end CFG_LATP_VITAL;


----- CELL LATPC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LATPC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (961.030 ps, 954.510 ps);
      tpd_GB_Q                       :	VitalDelayType01 := (1399.670 ps, 1244.420 ps);
      tpd_PRB_Q                      :	VitalDelayType01 := (279.160 ps, 625.340 ps);
      tpd_CLB_Q                      :	VitalDelayType01 := (279.160 ps, 625.340 ps);
      tpd_D_QB                       :	VitalDelayType01 := (1264.200 ps, 1219.990 ps);
      tpd_GB_QB                      :	VitalDelayType01 := (1687.280 ps, 1484.680 ps);
      tpd_PRB_QB                     :	VitalDelayType01 := (100.000 ps, 489.970 ps);
      tpd_CLB_QB                     :	VitalDelayType01 := (907.590 ps, 100.000 ps);
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_GB                        :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_PRB                       :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_CLB                       :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      D                              :	in    STD_ULOGIC;
      GB                             :	in    STD_ULOGIC;
      PRB                            :	in    STD_ULOGIC;
      CLB                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC;
      QB                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LATPC : entity is TRUE;
end LATPC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of LATPC is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL GB_ipd	 : STD_ULOGIC := 'X';
   SIGNAL PRB_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLB_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (GB_ipd, GB, tipd_GB);
   VitalWireDelay (PRB_ipd, PRB, tipd_PRB);
   VitalWireDelay (CLB_ipd, CLB, tipd_CLB);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, GB_ipd, PRB_ipd, CLB_ipd)


   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE PrevData_QB : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   ALIAS QB_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;
   VARIABLE QB_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------

      -- no timing checks

      -------------------------
      --  Functionality Section
      -------------------------
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => LATPC_Q_tab,
        DataIn => (
               CLB_ipd, GB_ipd, D_ipd, PRB_ipd));
      VitalStateTable(
        Result => QB_zd,
        PreviousDataIn => PrevData_QB,
        StateTable => LATPC_QB_tab,
        DataIn => (
               PRB_ipd, GB_ipd, D_ipd, CLB_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE),
                 1 => (GB_ipd'last_event, tpd_GB_Q, TRUE),
                 2 => (PRB_ipd'last_event, tpd_PRB_Q, TRUE),
                 3 => (CLB_ipd'last_event, tpd_CLB_Q, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => QB,
       GlitchData => QB_GlitchData,
       OutSignalName => "QB",
       OutTemp => QB_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_QB, TRUE),
                 1 => (GB_ipd'last_event, tpd_GB_QB, TRUE),
                 2 => (PRB_ipd'last_event, tpd_PRB_QB, TRUE),
                 3 => (CLB_ipd'last_event, tpd_CLB_QB, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LATPC_VITAL of LATPC is
   for VITAL
   end for;
end CFG_LATPC_VITAL;


----- CELL MUX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (690.380 ps, 714.350 ps);
      tpd_B_outb                     :	VitalDelayType01 := (724.830 ps, 735.190 ps);
      tpd_SEL_outb                   :	VitalDelayType01 := (662.750 ps, 742.990 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_SEL                       :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      SEL                            :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUX2 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end MUX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of MUX2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SEL_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   VitalWireDelay (SEL_ipd, SEL, tipd_SEL);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd, SEL_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := VitalMUX
                 (data => (A_ipd, B_ipd),
                  dselect => (0 => SEL_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE),
                 1 => (B_ipd'last_event, tpd_B_outb, TRUE),
                 2 => (SEL_ipd'last_event, tpd_SEL_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUX2_VITAL of MUX2 is
   for VITAL
   end for;
end CFG_MUX2_VITAL;


----- CELL NAND2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAND2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (170.120 ps, 215.380 ps);
      tpd_B_outb                     :	VitalDelayType01 := (160.430 ps, 205.670 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAND2 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end NAND2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NAND2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (NOT ((B_ipd) AND (A_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE),
                 1 => (B_ipd'last_event, tpd_B_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NAND2_VITAL of NAND2 is
   for VITAL
   end for;
end CFG_NAND2_VITAL;


----- CELL NAND2C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAND2C is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_out1                     :	VitalDelayType01 := (209.250 ps, 291.390 ps);
      tpd_B_out1                     :	VitalDelayType01 := (219.340 ps, 297.390 ps);
      tpd_A_out2                     :	VitalDelayType01 := (534.840 ps, 399.520 ps);
      tpd_B_out2                     :	VitalDelayType01 := (539.370 ps, 410.850 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      out1                           :	out   STD_ULOGIC;
      out2                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAND2C : entity is TRUE;
end NAND2C;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NAND2C is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS out1_zd : STD_LOGIC is Results(1);
   ALIAS out2_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE out1_GlitchData	: VitalGlitchDataType;
   VARIABLE out2_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      out1_zd := (NOT ((B_ipd) AND (A_ipd)));
      out2_zd := (B_ipd) AND (A_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => out1,
       GlitchData => out1_GlitchData,
       OutSignalName => "out1",
       OutTemp => out1_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out1, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out1, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => out2,
       GlitchData => out2_GlitchData,
       OutSignalName => "out2",
       OutTemp => out2_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out2, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out2, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NAND2C_VITAL of NAND2C is
   for VITAL
   end for;
end CFG_NAND2C_VITAL;


----- CELL NAND3 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAND3 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (238.450 ps, 418.700 ps);
      tpd_B_outb                     :	VitalDelayType01 := (238.230 ps, 411.670 ps);
      tpd_C_outb                     :	VitalDelayType01 := (210.960 ps, 391.990 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_C                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAND3 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end NAND3;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NAND3 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   VitalWireDelay (C_ipd, C, tipd_C);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd, C_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (NOT ((B_ipd) AND (A_ipd) AND (C_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE),
                 1 => (B_ipd'last_event, tpd_B_outb, TRUE),
                 2 => (C_ipd'last_event, tpd_C_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NAND3_VITAL of NAND3 is
   for VITAL
   end for;
end CFG_NAND3_VITAL;


----- CELL NAND3C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAND3C is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_out1                     :	VitalDelayType01 := (282.720 ps, 517.310 ps);
      tpd_B_out1                     :	VitalDelayType01 := (268.440 ps, 516.930 ps);
      tpd_C_out1                     :	VitalDelayType01 := (262.570 ps, 497.940 ps);
      tpd_A_out2                     :	VitalDelayType01 := (852.730 ps, 466.010 ps);
      tpd_B_out2                     :	VitalDelayType01 := (808.550 ps, 452.120 ps);
      tpd_C_out2                     :	VitalDelayType01 := (838.570 ps, 482.040 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_C                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      out1                           :	out   STD_ULOGIC;
      out2                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAND3C : entity is TRUE;
end NAND3C;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NAND3C is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   VitalWireDelay (C_ipd, C, tipd_C);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd, C_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS out1_zd : STD_LOGIC is Results(1);
   ALIAS out2_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE out1_GlitchData	: VitalGlitchDataType;
   VARIABLE out2_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      out1_zd := (NOT ((B_ipd) AND (A_ipd) AND (C_ipd)));
      out2_zd := (B_ipd) AND (A_ipd) AND (C_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => out1,
       GlitchData => out1_GlitchData,
       OutSignalName => "out1",
       OutTemp => out1_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out1, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out1, TRUE),
                 2 => (C_ipd'last_event, tpd_C_out1, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => out2,
       GlitchData => out2_GlitchData,
       OutSignalName => "out2",
       OutTemp => out2_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out2, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out2, TRUE),
                 2 => (C_ipd'last_event, tpd_C_out2, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NAND3C_VITAL of NAND3C is
   for VITAL
   end for;
end CFG_NAND3C_VITAL;


----- CELL NAND4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAND4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (256.650 ps, 564.250 ps);
      tpd_B_outb                     :	VitalDelayType01 := (248.930 ps, 561.040 ps);
      tpd_C_outb                     :	VitalDelayType01 := (227.350 ps, 542.560 ps);
      tpd_D_outb                     :	VitalDelayType01 := (224.720 ps, 510.020 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_C                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAND4 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end NAND4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NAND4 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (D_ipd, D, tipd_D);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (NOT ((B_ipd) AND (A_ipd) AND (C_ipd) AND (D_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE),
                 1 => (B_ipd'last_event, tpd_B_outb, TRUE),
                 2 => (C_ipd'last_event, tpd_C_outb, TRUE),
                 3 => (D_ipd'last_event, tpd_D_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NAND4_VITAL of NAND4 is
   for VITAL
   end for;
end CFG_NAND4_VITAL;


----- CELL NAND4C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NAND4C is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_out1                     :	VitalDelayType01 := (299.790 ps, 695.020 ps);
      tpd_B_out1                     :	VitalDelayType01 := (290.950 ps, 690.690 ps);
      tpd_C_out1                     :	VitalDelayType01 := (279.570 ps, 670.230 ps);
      tpd_D_out1                     :	VitalDelayType01 := (302.000 ps, 635.750 ps);
      tpd_A_out2                     :	VitalDelayType01 := (1060.930 ps, 486.440 ps);
      tpd_B_out2                     :	VitalDelayType01 := (1055.040 ps, 470.520 ps);
      tpd_C_out2                     :	VitalDelayType01 := (1004.560 ps, 454.790 ps);
      tpd_D_out2                     :	VitalDelayType01 := (976.920 ps, 495.330 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_C                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      out1                           :	out   STD_ULOGIC;
      out2                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NAND4C : entity is TRUE;
end NAND4C;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NAND4C is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (D_ipd, D, tipd_D);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS out1_zd : STD_LOGIC is Results(1);
   ALIAS out2_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE out1_GlitchData	: VitalGlitchDataType;
   VARIABLE out2_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      out1_zd := (NOT ((B_ipd) AND (A_ipd) AND (C_ipd) AND (D_ipd)));
      out2_zd := (B_ipd) AND (A_ipd) AND (C_ipd) AND (D_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => out1,
       GlitchData => out1_GlitchData,
       OutSignalName => "out1",
       OutTemp => out1_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out1, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out1, TRUE),
                 2 => (C_ipd'last_event, tpd_C_out1, TRUE),
                 3 => (D_ipd'last_event, tpd_D_out1, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => out2,
       GlitchData => out2_GlitchData,
       OutSignalName => "out2",
       OutTemp => out2_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out2, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out2, TRUE),
                 2 => (C_ipd'last_event, tpd_C_out2, TRUE),
                 3 => (D_ipd'last_event, tpd_D_out2, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NAND4C_VITAL of NAND4C is
   for VITAL
   end for;
end CFG_NAND4C_VITAL;


----- CELL NOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (306.120 ps, 180.470 ps);
      tpd_B_outb                     :	VitalDelayType01 := (246.340 ps, 144.220 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR2 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end NOR2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NOR2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (NOT ((B_ipd) OR (A_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE),
                 1 => (B_ipd'last_event, tpd_B_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NOR2_VITAL of NOR2 is
   for VITAL
   end for;
end CFG_NOR2_VITAL;


----- CELL NOR2C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR2C is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_out1                     :	VitalDelayType01 := (348.620 ps, 170.630 ps);
      tpd_B_out1                     :	VitalDelayType01 := (419.440 ps, 218.670 ps);
      tpd_A_out2                     :	VitalDelayType01 := (416.760 ps, 550.810 ps);
      tpd_B_out2                     :	VitalDelayType01 := (412.490 ps, 641.700 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      out1                           :	out   STD_ULOGIC;
      out2                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR2C : entity is TRUE;
end NOR2C;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NOR2C is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS out1_zd : STD_LOGIC is Results(1);
   ALIAS out2_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE out1_GlitchData	: VitalGlitchDataType;
   VARIABLE out2_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      out1_zd := (NOT ((B_ipd) OR (A_ipd)));
      out2_zd := (B_ipd) OR (A_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => out1,
       GlitchData => out1_GlitchData,
       OutSignalName => "out1",
       OutTemp => out1_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out1, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out1, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => out2,
       GlitchData => out2_GlitchData,
       OutSignalName => "out2",
       OutTemp => out2_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out2, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out2, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NOR2C_VITAL of NOR2C is
   for VITAL
   end for;
end CFG_NOR2C_VITAL;


----- CELL NOR3 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR3 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (638.190 ps, 237.180 ps);
      tpd_B_outb                     :	VitalDelayType01 := (598.690 ps, 221.450 ps);
      tpd_C_outb                     :	VitalDelayType01 := (410.680 ps, 164.140 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_C                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR3 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end NOR3;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NOR3 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   VitalWireDelay (C_ipd, C, tipd_C);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd, C_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (NOT ((B_ipd) OR (A_ipd) OR (C_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE),
                 1 => (B_ipd'last_event, tpd_B_outb, TRUE),
                 2 => (C_ipd'last_event, tpd_C_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NOR3_VITAL of NOR3 is
   for VITAL
   end for;
end CFG_NOR3_VITAL;


----- CELL NOR3C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR3C is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_out1                     :	VitalDelayType01 := (827.690 ps, 275.870 ps);
      tpd_B_out1                     :	VitalDelayType01 := (750.880 ps, 258.730 ps);
      tpd_C_out1                     :	VitalDelayType01 := (594.940 ps, 211.280 ps);
      tpd_A_out2                     :	VitalDelayType01 := (507.750 ps, 1086.060 ps);
      tpd_B_out2                     :	VitalDelayType01 := (500.950 ps, 1025.620 ps);
      tpd_C_out2                     :	VitalDelayType01 := (419.950 ps, 861.840 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_C                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      out1                           :	out   STD_ULOGIC;
      out2                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR3C : entity is TRUE;
end NOR3C;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NOR3C is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   VitalWireDelay (C_ipd, C, tipd_C);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd, C_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS out1_zd : STD_LOGIC is Results(1);
   ALIAS out2_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE out1_GlitchData	: VitalGlitchDataType;
   VARIABLE out2_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      out1_zd := (NOT ((B_ipd) OR (A_ipd) OR (C_ipd)));
      out2_zd := (B_ipd) OR (A_ipd) OR (C_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => out1,
       GlitchData => out1_GlitchData,
       OutSignalName => "out1",
       OutTemp => out1_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out1, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out1, TRUE),
                 2 => (C_ipd'last_event, tpd_C_out1, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => out2,
       GlitchData => out2_GlitchData,
       OutSignalName => "out2",
       OutTemp => out2_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out2, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out2, TRUE),
                 2 => (C_ipd'last_event, tpd_C_out2, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NOR3C_VITAL of NOR3C is
   for VITAL
   end for;
end CFG_NOR3C_VITAL;


----- CELL NOR4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (936.830 ps, 227.580 ps);
      tpd_B_outb                     :	VitalDelayType01 := (880.970 ps, 239.880 ps);
      tpd_C_outb                     :	VitalDelayType01 := (730.940 ps, 212.470 ps);
      tpd_D_outb                     :	VitalDelayType01 := (465.420 ps, 169.030 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_C                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR4 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end NOR4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NOR4 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (D_ipd, D, tipd_D);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (NOT ((B_ipd) OR (A_ipd) OR (C_ipd) OR (D_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE),
                 1 => (B_ipd'last_event, tpd_B_outb, TRUE),
                 2 => (C_ipd'last_event, tpd_C_outb, TRUE),
                 3 => (D_ipd'last_event, tpd_D_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NOR4_VITAL of NOR4 is
   for VITAL
   end for;
end CFG_NOR4_VITAL;


----- CELL NOR4C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity NOR4C is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_out1                     :	VitalDelayType01 := (1075.770 ps, 270.380 ps);
      tpd_B_out1                     :	VitalDelayType01 := (927.680 ps, 250.670 ps);
      tpd_C_out1                     :	VitalDelayType01 := (685.590 ps, 203.320 ps);
      tpd_D_out1                     :	VitalDelayType01 := (1134.410 ps, 269.150 ps);
      tpd_A_out2                     :	VitalDelayType01 := (492.230 ps, 1338.910 ps);
      tpd_B_out2                     :	VitalDelayType01 := (490.670 ps, 1200.570 ps);
      tpd_C_out2                     :	VitalDelayType01 := (421.030 ps, 948.620 ps);
      tpd_D_out2                     :	VitalDelayType01 := (513.930 ps, 1385.250 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_C                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_D                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      out1                           :	out   STD_ULOGIC;
      out2                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NOR4C : entity is TRUE;
end NOR4C;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of NOR4C is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   VitalWireDelay (C_ipd, C, tipd_C);
   VitalWireDelay (D_ipd, D, tipd_D);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS out1_zd : STD_LOGIC is Results(1);
   ALIAS out2_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE out1_GlitchData	: VitalGlitchDataType;
   VARIABLE out2_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      out1_zd := (NOT ((B_ipd) OR (A_ipd) OR (C_ipd) OR (D_ipd)));
      out2_zd := (B_ipd) OR (A_ipd) OR (C_ipd) OR (D_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => out1,
       GlitchData => out1_GlitchData,
       OutSignalName => "out1",
       OutTemp => out1_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out1, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out1, TRUE),
                 2 => (C_ipd'last_event, tpd_C_out1, TRUE),
                 3 => (D_ipd'last_event, tpd_D_out1, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => out2,
       GlitchData => out2_GlitchData,
       OutSignalName => "out2",
       OutTemp => out2_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_out2, TRUE),
                 1 => (B_ipd'last_event, tpd_B_out2, TRUE),
                 2 => (C_ipd'last_event, tpd_C_out2, TRUE),
                 3 => (D_ipd'last_event, tpd_D_out2, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NOR4C_VITAL of NOR4C is
   for VITAL
   end for;
end CFG_NOR4C_VITAL;


----- CELL SINV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity SINV is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb                     :	VitalDelayType01 := (395.840 ps, 350.680 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of SINV : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end SINV;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of SINV is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (NOT A_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_SINV_VITAL of SINV is
   for VITAL
   end for;
end CFG_SINV_VITAL;


----- CELL XNOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity XNOR2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb_B_EQ_1              :	VitalDelayType01 := (581.840 ps, 523.040 ps);
      tpd_A_outb_B_EQ_0              :	VitalDelayType01 := (581.840 ps, 523.040 ps);
      tpd_A_outb                     :	VitalDelayType01 := (581.840 ps, 523.040 ps);
      tpd_B_outb_A_EQ_1              :	VitalDelayType01 := (345.970 ps, 266.650 ps);
      tpd_B_outb_A_EQ_0              :	VitalDelayType01 := (345.970 ps, 266.650 ps);
      tpd_B_outb                     :	VitalDelayType01 := (345.970 ps, 266.650 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of XNOR2 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end XNOR2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of XNOR2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (NOT ((B_ipd) XOR (A_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb_B_EQ_1,
                        (TO_X01(B_ipd)='1')),
                 1 => (A_ipd'last_event, tpd_A_outb_B_EQ_0,
                        (TO_X01((NOT B_ipd))='1')),
                 2 => (A_ipd'last_event, tpd_A_outb,
                        (TO_X01((B_ipd) OR ((NOT B_ipd)))/='1')),
                 3 => (B_ipd'last_event, tpd_B_outb_A_EQ_1,
                        (TO_X01(A_ipd)='1')),
                 4 => (B_ipd'last_event, tpd_B_outb_A_EQ_0,
                        (TO_X01((NOT A_ipd))='1')),
                 5 => (B_ipd'last_event, tpd_B_outb,
                        (TO_X01((A_ipd) OR ((NOT A_ipd)))/='1'))),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_XNOR2_VITAL of XNOR2 is
   for VITAL
   end for;
end CFG_XNOR2_VITAL;


----- CELL XOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity XOR2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A_outb_B_EQ_1              :	VitalDelayType01 := (353.260 ps, 325.270 ps);
      tpd_A_outb_B_EQ_0              :	VitalDelayType01 := (353.260 ps, 325.270 ps);
      tpd_A_outb                     :	VitalDelayType01 := (353.260 ps, 325.270 ps);
      tpd_B_outb_A_EQ_1              :	VitalDelayType01 := (563.810 ps, 785.000 ps);
      tpd_B_outb_A_EQ_0              :	VitalDelayType01 := (563.810 ps, 785.000 ps);
      tpd_B_outb                     :	VitalDelayType01 := (563.810 ps, 785.000 ps);
      tipd_A                         :	VitalDelayType01 := (0.000 ps, 0.000 ps);
      tipd_B                         :	VitalDelayType01 := (0.000 ps, 0.000 ps));

   port(
      A                              :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      outb                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of XOR2 : entity is TRUE;

   -- real names
   -- REAL_NAME of outb is "out"
end XOR2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library mAMIs050DL;
use mAMIs050DL.VTABLES.all;
architecture VITAL of XOR2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A_ipd, A, tipd_A);
   VitalWireDelay (B_ipd, B, tipd_B);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A_ipd, B_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS outb_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE outb_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      outb_zd := (B_ipd) XOR (A_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => outb,
       GlitchData => outb_GlitchData,
       OutSignalName => "outb",
       OutTemp => outb_zd,
       Paths => (0 => (A_ipd'last_event, tpd_A_outb_B_EQ_1,
                        (TO_X01(B_ipd)='1')),
                 1 => (A_ipd'last_event, tpd_A_outb_B_EQ_0,
                        (TO_X01((NOT B_ipd))='1')),
                 2 => (A_ipd'last_event, tpd_A_outb,
                        (TO_X01((B_ipd) OR ((NOT B_ipd)))/='1')),
                 3 => (B_ipd'last_event, tpd_B_outb_A_EQ_1,
                        (TO_X01(A_ipd)='1')),
                 4 => (B_ipd'last_event, tpd_B_outb_A_EQ_0,
                        (TO_X01((NOT A_ipd))='1')),
                 5 => (B_ipd'last_event, tpd_B_outb,
                        (TO_X01((A_ipd) OR ((NOT A_ipd)))/='1'))),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_XOR2_VITAL of XOR2 is
   for VITAL
   end for;
end CFG_XOR2_VITAL;


---- end of library ----
