Update History
MOSIS HP 0.5um - Submicron Rules
Hi-ESD_IO Pad
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12NovOct2001
- Updated to current Mosis technology setup V8.0
- Horizontally flip PADBIDIRHE to correct Pad ports order.
- Added Poly in Bond Pad to increase Poly density.
- Updated DIUNBUF port
- Matched transistors size between layout and schematic cells 
 
23Feb2001
- Updated Ports and PadVdd

25Aug2000
- Updated SPR Design rules setup.
- Changed port Data in padio from via2 to metal2
 
13Oct99

- Update DRC Rule 8.5, 9.2 
- Change recognition layer of devices to small case
- Added capacitances and resistances base on Mosis Parametric Test Results
  Run: N98R, Technology: SCN05H for Mosis HP 0.5 Submicron Process.

			 
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